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| author | Jim Grosbach <grosbach@apple.com> | 2009-10-23 23:07:42 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2009-10-23 23:07:42 +0000 |
| commit | 22b2c011f99845cbb9b64ef02d2699858b67e602 (patch) | |
| tree | 472b82096b6f61fa455f2336ec6577d2db67e994 | |
| parent | 48f2d5860d8a86107e6553f845b355886587885a (diff) | |
| download | bcm5719-llvm-22b2c011f99845cbb9b64ef02d2699858b67e602.tar.gz bcm5719-llvm-22b2c011f99845cbb9b64ef02d2699858b67e602.zip | |
FIXME no longer applies. R12 and R3 are available for allocation
llvm-svn: 84977
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterInfo.td | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td index e0be7843297..9a0111d9d89 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.td +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td @@ -129,9 +129,6 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; - // FIXME: We are reserving r12 in case the PEI needs to use it to - // generate large stack offset. Make it available once we have register - // scavenging. Similarly r3 is reserved in Thumb mode for now. let MethodBodies = [{ // FP is R11, R9 is available. static const unsigned ARM_GPR_AO_1[] = { |
