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author | Craig Topper <craig.topper@intel.com> | 2018-02-26 02:16:34 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2018-02-26 02:16:34 +0000 |
commit | 2286058f4659ff28ae3883194d5a75c819742c3c (patch) | |
tree | af124e3d18d38a24597f413aaf1a87647be0ad2d | |
parent | 2bf8e3e0e191bd434b867133d0ee093eec63edfb (diff) | |
download | bcm5719-llvm-2286058f4659ff28ae3883194d5a75c819742c3c.tar.gz bcm5719-llvm-2286058f4659ff28ae3883194d5a75c819742c3c.zip |
[X86] Use SelectionDAG::SplitVectorOperand to simplify some code. NFC
llvm-svn: 326065
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e1fc9a2d514..504bee73fe2 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -25134,13 +25134,9 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, // we can split using the k-register rather than memory. if (SrcVT == MVT::v64i1 && DstVT == MVT::i64 && Subtarget.hasBWI()) { assert(!Subtarget.is64Bit() && "Expected 32-bit mode"); - SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v32i1, - N->getOperand(0), - DAG.getIntPtrConstant(0, dl)); + SDValue Lo, Hi; + std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0); Lo = DAG.getBitcast(MVT::i32, Lo); - SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v32i1, - N->getOperand(0), - DAG.getIntPtrConstant(32, dl)); Hi = DAG.getBitcast(MVT::i32, Hi); SDValue Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); Results.push_back(Res); |