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authorCraig Topper <craig.topper@intel.com>2018-07-09 16:02:59 +0000
committerCraig Topper <craig.topper@intel.com>2018-07-09 16:02:59 +0000
commit22330c700b4769fe476e541b0afbdcf08197df01 (patch)
tree15d2b3eb440fc3d6f62f942c11d6da92df9ae9b4
parentd09530144a5412a01d222a77257ab2be12d977f1 (diff)
downloadbcm5719-llvm-22330c700b4769fe476e541b0afbdcf08197df01.tar.gz
bcm5719-llvm-22330c700b4769fe476e541b0afbdcf08197df01.zip
[X86] Remove some seemingly unnecessary AddedComplexity lines.
Looking at the generated tables this didn't seem to make an obvious difference in pattern priority. llvm-svn: 336555
-rw-r--r--llvm/lib/Target/X86/X86InstrSSE.td12
1 files changed, 4 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 0af72817b8d..4644c62666c 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -711,9 +711,7 @@ multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
"\t{$src2, $dst|$dst, $src2}">;
}
-let AddedComplexity = 20 in {
- defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp">;
-}
+defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp">;
let SchedRW = [WriteFStore] in {
let Predicates = [UseAVX] in {
@@ -796,9 +794,7 @@ let Predicates = [UseSSE2] in {
// SSE 1 & 2 - Move Hi packed FP Instructions
//===----------------------------------------------------------------------===//
-let AddedComplexity = 20 in {
- defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Unpckl, "movhp">;
-}
+defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Unpckl, "movhp">;
let SchedRW = [WriteFStore] in {
// v2f64 extract element 1 is always custom lowered to unpack high to low
@@ -889,7 +885,7 @@ let Predicates = [UseSSE2] in {
// SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
//===----------------------------------------------------------------------===//
-let AddedComplexity = 20, Predicates = [UseAVX] in {
+let Predicates = [UseAVX] in {
def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
"movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
@@ -904,7 +900,7 @@ let AddedComplexity = 20, Predicates = [UseAVX] in {
VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG,
NotMemoryFoldable;
}
-let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
+let Constraints = "$src1 = $dst" in {
def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
"movlhps\t{$src2, $dst|$dst, $src2}",
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