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| author | Chandler Carruth <chandlerc@gmail.com> | 2014-09-21 13:37:51 +0000 |
|---|---|---|
| committer | Chandler Carruth <chandlerc@gmail.com> | 2014-09-21 13:37:51 +0000 |
| commit | 215037e35d869c2d2f7c2506ae74404b8e40c264 (patch) | |
| tree | 96e91abc32ad5acc64888eb48f3e28c4c296337a | |
| parent | b3125c7522321767dc4641c69a2352b36b9619f3 (diff) | |
| download | bcm5719-llvm-215037e35d869c2d2f7c2506ae74404b8e40c264.tar.gz bcm5719-llvm-215037e35d869c2d2f7c2506ae74404b8e40c264.zip | |
[x86] With the stronger canonicalization of shuffles added in r218216,
the new vector shuffle lowering no longer needs to check both symmetric
forms of UNPCK patterns for v4f64.
llvm-svn: 218217
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 2a020b51001..c2f8427df0a 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -9257,10 +9257,6 @@ static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2, return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2); if (isShuffleEquivalent(Mask, 1, 5, 3, 7)) return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2); - if (isShuffleEquivalent(Mask, 4, 0, 6, 2)) - return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1); - if (isShuffleEquivalent(Mask, 5, 1, 7, 3)) - return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1); // If we have a single input to the zero element, insert that into V1 if we // can do so cheaply. |
