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authorAkira Hatanaka <ahatanaka@mips.com>2011-09-30 19:18:24 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-09-30 19:18:24 +0000
commit1fef284cf99941f499daa17a4c162fa1171a7468 (patch)
tree1230a92449fd2d91b9d2c67264dd3bca618edd10
parent271002fc9928c04aa9319b1a537b6771c87c06e3 (diff)
downloadbcm5719-llvm-1fef284cf99941f499daa17a4c162fa1171a7468.tar.gz
bcm5719-llvm-1fef284cf99941f499daa17a4c162fa1171a7468.zip
Remove unnecessary checking of register operands.
llvm-svn: 140872
-rw-r--r--llvm/test/CodeGen/Mips/madd-msub.ll12
-rw-r--r--llvm/test/CodeGen/Mips/rotate.ll2
2 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/Mips/madd-msub.ll b/llvm/test/CodeGen/Mips/madd-msub.ll
index 9dde98d51b1..0aeabb30e28 100644
--- a/llvm/test/CodeGen/Mips/madd-msub.ll
+++ b/llvm/test/CodeGen/Mips/madd-msub.ll
@@ -1,6 +1,6 @@
; RUN: llc -march=mips < %s | FileCheck %s
-; CHECK: madd $5, $4
+; CHECK: madd
define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64
@@ -11,7 +11,7 @@ entry:
ret i64 %add
}
-; CHECK: maddu $5, $4
+; CHECK: maddu
define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = zext i32 %a to i64
@@ -22,7 +22,7 @@ entry:
ret i64 %add
}
-; CHECK: madd $5, $4
+; CHECK: madd
define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64
@@ -32,7 +32,7 @@ entry:
ret i64 %add
}
-; CHECK: msub $5, $4
+; CHECK: msub
define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = sext i32 %c to i64
@@ -43,7 +43,7 @@ entry:
ret i64 %sub
}
-; CHECK: msubu $5, $4
+; CHECK: msubu
define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = zext i32 %c to i64
@@ -54,7 +54,7 @@ entry:
ret i64 %sub
}
-; CHECK: msub $5, $4
+; CHECK: msub
define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64
diff --git a/llvm/test/CodeGen/Mips/rotate.ll b/llvm/test/CodeGen/Mips/rotate.ll
index e7dc3093214..8e27f4aad6e 100644
--- a/llvm/test/CodeGen/Mips/rotate.ll
+++ b/llvm/test/CodeGen/Mips/rotate.ll
@@ -1,6 +1,6 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
-; CHECK: rotrv $2, $4, $2
+; CHECK: rotrv $2, $4
define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
entry:
%shl = shl i32 %a, %b
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