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| author | Sanjay Patel <spatel@rotateright.com> | 2019-04-17 16:02:07 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-04-17 16:02:07 +0000 |
| commit | 1f2c81af72bdf6175c1f3f7e7628c24d83e15e74 (patch) | |
| tree | 0d455ab012fcdf04f33aaca6cd994232d87fc3a6 | |
| parent | 893aea58ea5ead1433658f181fd5bd749fe21a92 (diff) | |
| download | bcm5719-llvm-1f2c81af72bdf6175c1f3f7e7628c24d83e15e74.tar.gz bcm5719-llvm-1f2c81af72bdf6175c1f3f7e7628c24d83e15e74.zip | |
[ARM] make test checks more thorough; NFC
This will change with the proposal in D60214.
Unfortunately, the triple is not supported for auto-generation
via script, and the multiple RUN lines have diffs on this test,
but I can't tell exactly what is required by this test.
PR7162 was an assert/crash, so hopefully, this is good enough.
llvm-svn: 358587
| -rw-r--r-- | llvm/test/CodeGen/ARM/reg_sequence.ll | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index a54dd0fe79f..bddd9344b3c 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -270,11 +270,23 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; PR7162 define arm_aapcs_vfpcc i32 @t10(float %x) nounwind { -entry: ; CHECK-LABEL: t10: -; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000 -; CHECK: vmul.f32 q8, q9, d1[0] -; CHECK: vadd.f32 q8, q8, q8 +; CHECK: vdup.32 [[Q0:q[0-9]+]], d0[0] +; CHECK: vmov.i32 [[Q9:q[0-9]+]], #0x3f000000 +; CHECK: vmul.f32 [[Q8:q[0-9]+]], [[Q0]], [[Q0]] +; CHECK: vadd.f32 [[Q8]], [[Q8]], [[Q8]] +; CHECK: vadd.f32 [[Q1:q[0-9]+]], [[Q8]], [[Q8]] +; CHECK: vmul.f32 [[Q8]], [[Q9]], d1[0] +; CHECK: vmul.f32 [[Q8]], [[Q8]], [[Q8]] +; CHECK: vadd.f32 [[Q8]], [[Q8]], [[Q8]] +; CHECK: vmul.f32 [[Q8]], [[Q8]], [[Q8]] +; CHECK: vst1.32 {d17[1]}, [r0:32] +; CHECK: mov r0, #0 +; CHECK: cmp r0, #0 +; CHECK: movne r0, #0 +; CHECK: bxne lr +; CHECK: trap +entry: %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float %x, i32 1 ; <<4 x float>> [#uses=1] %2 = insertelement <4 x float> %1, float %x, i32 2 ; <<4 x float>> [#uses=1] |
