[InstCombine] consolidate tests for related bugs

llvm-svn: 265973

2 files changed, 32 insertions, 26 deletions

diff --git a/llvm/test/Transforms/InstCombine/pr8547.ll b/llvm/test/Transforms/InstCombine/pr8547.ll
deleted file mode 100644
index 6d74b4002c1..00000000000
--- a/llvm/test/Transforms/InstCombine/pr8547.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: opt < %s -instcombine -S | FileCheck %s
-; Converting the 2 shifts to SHL 6 without the AND is wrong.  PR 8547.
-
-@g_2 = global i32 0, align 4
-@.str = constant [10 x i8] c"g_2 = %d\0A\00"
-
-declare i32 @printf(i8*, ...)
-
-define i32 @main() nounwind {
-codeRepl:
-  br label %for.cond
-
-for.cond:                                         ; preds = %for.cond, %codeRepl
-  %storemerge = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
-  store i32 %storemerge, i32* @g_2, align 4
-  %shl = shl i32 %storemerge, 30
-  %conv2 = lshr i32 %shl, 24
-; CHECK:  %0 = shl nuw nsw i32 %storemerge, 6
-; CHECK:  %conv2 = and i32 %0, 64
-  %tobool = icmp eq i32 %conv2, 0
-  br i1 %tobool, label %for.cond, label %codeRepl2
-
-codeRepl2:                                        ; preds = %for.cond
-  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i64 0, i64 0), i32 %conv2) nounwind
-  ret i32 0
-}
diff --git a/llvm/test/Transforms/InstCombine/shift-shift.ll b/llvm/test/Transforms/InstCombine/shift-shift.ll
index 2968a9bf3c6..6aa262fd931 100644
--- a/llvm/test/Transforms/InstCombine/shift-shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift-shift.ll
@@ -41,3 +41,35 @@ loop:
   br label %loop
 }
 
+; Converting the 2 shifts to SHL 6 without the AND is wrong.
+; https://llvm.org/bugs/show_bug.cgi?id=8547
+
+define i32 @pr8547(i32* %g) {
+; CHECK-LABEL: @pr8547(
+; CHECK-NEXT:  codeRepl:
+; CHECK-NEXT:    br label %for.cond
+; CHECK:       for.cond:
+; CHECK-NEXT:    [[STOREMERGE:%.*]] = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
+; CHECK-NEXT:    store i32 [[STOREMERGE]], i32* %g, align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = shl nuw nsw i32 [[STOREMERGE]], 6
+; CHECK-NEXT:    [[CONV2:%.*]] = and i32 [[TMP0]], 64
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[CONV2]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL]], label %for.cond, label %codeRepl2
+; CHECK:       codeRepl2:
+; CHECK-NEXT:    ret i32 [[CONV2]]
+;
+codeRepl:
+  br label %for.cond
+
+for.cond:
+  %storemerge = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
+  store i32 %storemerge, i32* %g, align 4
+  %shl = shl i32 %storemerge, 30
+  %conv2 = lshr i32 %shl, 24
+  %tobool = icmp eq i32 %conv2, 0
+  br i1 %tobool, label %for.cond, label %codeRepl2
+
+codeRepl2:
+  ret i32 %conv2
+}
+