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authorCraig Topper <craig.topper@intel.com>2017-10-23 16:22:38 +0000
committerCraig Topper <craig.topper@intel.com>2017-10-23 16:22:38 +0000
commit1db2f0828ea6ef5a6fd0601de400d672c7c3849e (patch)
treee9f672fdeffb7db4ecc1d30aec49aa037ce66d8d
parent9ec60988cdc6e547fa30a2390d6269cb0ba9144b (diff)
downloadbcm5719-llvm-1db2f0828ea6ef5a6fd0601de400d672c7c3849e.tar.gz
bcm5719-llvm-1db2f0828ea6ef5a6fd0601de400d672c7c3849e.zip
[X86] Change RDRAND to use PS instead of TB.
Should be no functional change for now. A future disassembler change will prevent disassembling with 0xf2/0xf3. llvm-svn: 316339
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 05e47163c68..17b74d006ea 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -2180,13 +2180,13 @@ let Predicates = [HasMOVBE] in {
let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
"rdrand{w}\t$dst",
- [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
+ [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, PS;
def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
"rdrand{l}\t$dst",
- [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
+ [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, PS;
def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
"rdrand{q}\t$dst",
- [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
+ [(set GR64:$dst, EFLAGS, (X86rdrand))]>, PS;
}
//===----------------------------------------------------------------------===//
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