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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-07-02 10:22:14 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-07-02 10:22:14 +0000 |
| commit | 1d7d0e21263c09d41910c7d334b97a97085449a3 (patch) | |
| tree | 58bab6d429e45556ecb1e0af56d5a800c2fbe522 | |
| parent | 8cce399b9d438909557419a562168902cea0a4b0 (diff) | |
| download | bcm5719-llvm-1d7d0e21263c09d41910c7d334b97a97085449a3.tar.gz bcm5719-llvm-1d7d0e21263c09d41910c7d334b97a97085449a3.zip | |
[mips] Mark P5600 scheduling model as complete
llvm-svn: 364902
| -rw-r--r-- | llvm/lib/Target/Mips/MipsScheduleP5600.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td index 3eb0e3740bf..f97b03bff08 100644 --- a/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -12,7 +12,7 @@ def MipsP5600Model : SchedMachineModel { int LoadLatency = 4; int MispredictPenalty = 8; // TODO: Estimated - let CompleteModel = 0; + let CompleteModel = 1; let FullInstRWOverlapCheck = 1; list<Predicate> UnsupportedFeatures = [HasMips3, HasMips32r6, HasMips64, |
