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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-07-16 22:41:38 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-07-16 22:41:38 +0000
commit1bd9c6547f92e694d8d724efb757bc9e8b1f3607 (patch)
tree0b535b96912676e7045a94462c0e9b0cf1e86b38
parent1c3f4ec7fc1d0c58ec4024a064c055462448e50f (diff)
downloadbcm5719-llvm-1bd9c6547f92e694d8d724efb757bc9e8b1f3607.tar.gz
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ARM: Fix missing immarg for space intrinsic
llvm-svn: 366280
-rw-r--r--llvm/include/llvm/IR/IntrinsicsARM.td2
-rw-r--r--llvm/test/Verifier/ARM/intrinsic-immarg.ll9
2 files changed, 10 insertions, 1 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td
index 886f1d7fd1b..4792af097d9 100644
--- a/llvm/include/llvm/IR/IntrinsicsARM.td
+++ b/llvm/include/llvm/IR/IntrinsicsARM.td
@@ -19,7 +19,7 @@ let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
// A space-consuming intrinsic primarily for testing ARMConstantIslands. The
// first argument is the number of bytes this "instruction" takes up, the second
// and return value are essentially chains, used to force ordering during ISel.
-def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
+def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg<0>]>;
// 16-bit multiplications
def int_arm_smulbb : GCCBuiltin<"__builtin_arm_smulbb">,
diff --git a/llvm/test/Verifier/ARM/intrinsic-immarg.ll b/llvm/test/Verifier/ARM/intrinsic-immarg.ll
index b578c6d7619..d069dd682fd 100644
--- a/llvm/test/Verifier/ARM/intrinsic-immarg.ll
+++ b/llvm/test/Verifier/ARM/intrinsic-immarg.ll
@@ -100,3 +100,12 @@ define void @mcrr2(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
call void @llvm.arm.mcrr2(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
ret void
}
+
+declare i32 @llvm.arm.space(i32, i32) nounwind
+define i32 @space(i32 %arg0, i32 %arg1) {
+ ; CHECK: immarg operand has non-immediate parameter
+ ; CHECK-NEXT: i32 %arg0
+ ; CHECK-NEXT: call i32 @llvm.arm.space(i32 %arg0, i32 %arg1)
+ %space = call i32 @llvm.arm.space(i32 %arg0, i32 %arg1)
+ ret i32 %space
+}
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