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authorEvan Cheng <evan.cheng@apple.com>2010-04-15 18:42:28 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-04-15 18:42:28 +0000
commit1ba1428577a593612b80b6a7465a36d52b12cc70 (patch)
tree1ec24b8011d7dfcc83b7138f2c18942bd3a795a8
parent4230e35879bfa984a4910aac0baa5e3d11f6000a (diff)
downloadbcm5719-llvm-1ba1428577a593612b80b6a7465a36d52b12cc70.tar.gz
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ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
llvm is generating poor code for dynamic alloca, I'll fix that later. llvm-svn: 101383
-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp2
-rw-r--r--llvm/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll23
2 files changed, 24 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 7d486631897..2f24d2ea1c6 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -945,7 +945,7 @@ SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue Size = N->getOperand(1);
SDValue Align = N->getOperand(2);
- SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
+ SDValue SP = CurDAG->getCopyFromReg(Chain, dl, ARM::SP, MVT::i32);
int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
if (AlignVal < 0)
// We need to align the stack. Use Thumb1 tAND which is the only thumb
diff --git a/llvm/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll b/llvm/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
new file mode 100644
index 00000000000..329494b3219
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -O3 | FileCheck %s
+; rdar://7493908
+
+; Make sure the result of the first dynamic_alloc isn't copied back to sp more
+; than once. We'll deal with poor codegen later.
+
+define arm_apcscc void @t() nounwind ssp {
+entry:
+; CHECK: t:
+; CHECK: mvn r0, #7
+; CHECK: ands sp, r0
+; CHECK: mov r1, sp
+; CHECK: mov sp, r1
+; Yes, this is stupid codegen, but it's correct.
+; CHECK: sub sp, #16
+; CHECK: mov r1, sp
+; CHECK: mov sp, r1
+; CHECK: ands sp, r0
+ %size = mul i32 8, 2
+ %vla_a = alloca i8, i32 %size, align 8
+ %vla_b = alloca i8, i32 %size, align 8
+ unreachable
+}
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