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| author | Sanjay Patel <spatel@rotateright.com> | 2015-04-03 17:17:50 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2015-04-03 17:17:50 +0000 |
| commit | 1ad50ba966bcb1f628a30ab3782779c2e35c69b0 (patch) | |
| tree | b29c4e6aac754fdc69af60f40da62e1f1dd28851 | |
| parent | 9df9a67bdb9f7d0c006519d41c388eb0098de3fd (diff) | |
| download | bcm5719-llvm-1ad50ba966bcb1f628a30ab3782779c2e35c69b0.tar.gz bcm5719-llvm-1ad50ba966bcb1f628a30ab3782779c2e35c69b0.zip | |
use update_llc_test_checks.py to tighten checking; remove unnecessary testing params
llvm-svn: 234029
| -rw-r--r-- | llvm/test/CodeGen/X86/avx-cvt-2.ll | 52 |
1 files changed, 43 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/X86/avx-cvt-2.ll b/llvm/test/CodeGen/X86/avx-cvt-2.ll index 8cc7190fcc6..583c7d5947b 100644 --- a/llvm/test/CodeGen/X86/avx-cvt-2.ll +++ b/llvm/test/CodeGen/X86/avx-cvt-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s ; Check that we generate vector conversion from float to narrower int types @@ -8,8 +8,16 @@ define void @fptoui16(%f32vec_t %a, %i16vec_t *%p) { ; CHECK-LABEL: fptoui16: -; CHECK: vcvttps2dq %ymm -; CHECK-NOT: vcvttss2si +; CHECK: # BB#0: +; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0 +; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 +; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; CHECK-NEXT: vmovdqa %xmm0, (%rdi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq %b = fptoui %f32vec_t %a to %i16vec_t store %i16vec_t %b, %i16vec_t * %p ret void @@ -17,8 +25,16 @@ define void @fptoui16(%f32vec_t %a, %i16vec_t *%p) { define void @fptosi16(%f32vec_t %a, %i16vec_t *%p) { ; CHECK-LABEL: fptosi16: -; CHECK: vcvttps2dq %ymm -; CHECK-NOT: vcvttss2si +; CHECK: # BB#0: +; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0 +; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 +; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; CHECK-NEXT: vmovdqa %xmm0, (%rdi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq %b = fptosi %f32vec_t %a to %i16vec_t store %i16vec_t %b, %i16vec_t * %p ret void @@ -26,8 +42,17 @@ define void @fptosi16(%f32vec_t %a, %i16vec_t *%p) { define void @fptoui8(%f32vec_t %a, %i8vec_t *%p) { ; CHECK-LABEL: fptoui8: -; CHECK: vcvttps2dq %ymm -; CHECK-NOT: vcvttss2si +; CHECK: # BB#0: +; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0 +; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 +; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] +; CHECK-NEXT: vmovq %xmm0, (%rdi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq %b = fptoui %f32vec_t %a to %i8vec_t store %i8vec_t %b, %i8vec_t * %p ret void @@ -35,8 +60,17 @@ define void @fptoui8(%f32vec_t %a, %i8vec_t *%p) { define void @fptosi8(%f32vec_t %a, %i8vec_t *%p) { ; CHECK-LABEL: fptosi8: -; CHECK: vcvttps2dq %ymm -; CHECK-NOT: vcvttss2si +; CHECK: # BB#0: +; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0 +; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 +; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] +; CHECK-NEXT: vmovq %xmm0, (%rdi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq %b = fptosi %f32vec_t %a to %i8vec_t store %i8vec_t %b, %i8vec_t * %p ret void |
