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authorRoman Lebedev <lebedev.ri@gmail.com>2019-05-18 20:24:40 +0000
committerRoman Lebedev <lebedev.ri@gmail.com>2019-05-18 20:24:40 +0000
commit1a5d623ded8e0845d42c9ea272425a11391bf412 (patch)
treedb05bec94d1f51333a951031476461450300280a
parent13ac317e4cf91b5dc602482c430fdf30ef8b3971 (diff)
downloadbcm5719-llvm-1a5d623ded8e0845d42c9ea272425a11391bf412.tar.gz
bcm5719-llvm-1a5d623ded8e0845d42c9ea272425a11391bf412.zip
[NFC][AArch64] Autogenerate fcopysign.ll test
llvm-svn: 361106
-rw-r--r--llvm/test/CodeGen/AArch64/fcopysign.ll46
1 files changed, 31 insertions, 15 deletions
diff --git a/llvm/test/CodeGen/AArch64/fcopysign.ll b/llvm/test/CodeGen/AArch64/fcopysign.ll
index a625a9eb2a6..ebd91b3f3a2 100644
--- a/llvm/test/CodeGen/AArch64/fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/fcopysign.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -o - %s | FileCheck %s
; Check that selection dag legalization of fcopysign works in cases with
; different modes for the arguments.
@@ -9,14 +10,22 @@ declare fp128 @llvm.copysign.f128(fp128, fp128)
@val_double = global double zeroinitializer, align 8
@val_fp128 = global fp128 zeroinitializer, align 16
-; CHECK-LABEL: copysign0
-; CHECK: ldr [[REG:x[0-9]+]], [x8, :lo12:val_double]
-; CHECK: and [[ANDREG:x[0-9]+]], [[REG]], #0x8000000000000000
-; CHECK: lsr x[[LSRREGNUM:[0-9]+]], [[ANDREG]], #56
-; CHECK: bfxil w[[LSRREGNUM]], w{{[0-9]+}}, #0, #7
-; CHECK: strb w[[LSRREGNUM]],
-; CHECK: ldr q{{[0-9]+}},
define fp128 @copysign0() {
+; CHECK-LABEL: copysign0:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: adrp x8, .LCPI0_0
+; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT: adrp x8, val_double
+; CHECK-NEXT: str q0, [sp, #-16]!
+; CHECK-NEXT: ldr x8, [x8, :lo12:val_double]
+; CHECK-NEXT: ldrb w9, [sp, #15]
+; CHECK-NEXT: and x8, x8, #0x8000000000000000
+; CHECK-NEXT: lsr x8, x8, #56
+; CHECK-NEXT: bfxil w8, w9, #0, #7
+; CHECK-NEXT: strb w8, [sp, #15]
+; CHECK-NEXT: ldr q0, [sp], #16
+; CHECK-NEXT: ret
entry:
%v = load double, double* @val_double, align 8
%conv = fpext double %v to fp128
@@ -24,15 +33,22 @@ entry:
ret fp128 %call
}
-; CHECK-LABEL: copysign1
-; CHECK-DAG: ldr [[REG:q[0-9]+]], [x8, :lo12:val_fp128]
-; CHECK-DAG: ldr [[REG:w[0-9]+]], [x8, :lo12:val_float]
-; CHECK: and [[ANDREG:w[0-9]+]], [[REG]], #0x80000000
-; CHECK: lsr w[[LSRREGNUM:[0-9]+]], [[ANDREG]], #24
-; CHECK: bfxil w[[LSRREGNUM]], w{{[0-9]+}}, #0, #7
-; CHECK: strb w[[LSRREGNUM]],
-; CHECK: ldr q{{[0-9]+}},
define fp128@copysign1() {
+; CHECK-LABEL: copysign1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: adrp x8, val_fp128
+; CHECK-NEXT: ldr q0, [x8, :lo12:val_fp128]
+; CHECK-NEXT: adrp x8, val_float
+; CHECK-NEXT: str q0, [sp, #-16]!
+; CHECK-NEXT: ldr w8, [x8, :lo12:val_float]
+; CHECK-NEXT: ldrb w9, [sp, #15]
+; CHECK-NEXT: and w8, w8, #0x80000000
+; CHECK-NEXT: lsr w8, w8, #24
+; CHECK-NEXT: bfxil w8, w9, #0, #7
+; CHECK-NEXT: strb w8, [sp, #15]
+; CHECK-NEXT: ldr q0, [sp], #16
+; CHECK-NEXT: ret
entry:
%v0 = load fp128, fp128* @val_fp128, align 16
%v1 = load float, float* @val_float, align 4
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