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| author | Craig Topper <craig.topper@gmail.com> | 2017-04-17 01:51:24 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-04-17 01:51:24 +0000 |
| commit | 1a18a7c51e06f682223da2bab02e783acd5015cd (patch) | |
| tree | 8df0903c4baff529b882106af31ab7cf093c8b85 | |
| parent | b60f300afb374c65a90ebc6d96125a33e80f0034 (diff) | |
| download | bcm5719-llvm-1a18a7c51e06f682223da2bab02e783acd5015cd.tar.gz bcm5719-llvm-1a18a7c51e06f682223da2bab02e783acd5015cd.zip | |
[InstCombine] Add support for vector srem->urem.
llvm-svn: 300437
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/rem.ll | 2 |
2 files changed, 6 insertions, 8 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index de0c2a15b43..953e7f36467 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -1544,13 +1544,11 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) { // If the sign bits of both operands are zero (i.e. we can prove they are // unsigned inputs), turn this into a urem. - if (I.getType()->isIntegerTy()) { - APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); - if (MaskedValueIsZero(Op1, Mask, 0, &I) && - MaskedValueIsZero(Op0, Mask, 0, &I)) { - // X srem Y -> X urem Y, iff X and Y don't have sign bit set - return BinaryOperator::CreateURem(Op0, Op1, I.getName()); - } + APInt Mask(APInt::getSignBit(I.getType()->getScalarSizeInBits())); + if (MaskedValueIsZero(Op1, Mask, 0, &I) && + MaskedValueIsZero(Op0, Mask, 0, &I)) { + // X srem Y -> X urem Y, iff X and Y don't have sign bit set + return BinaryOperator::CreateURem(Op0, Op1, I.getName()); } // If it's a constant vector, flip any negative values positive. diff --git a/llvm/test/Transforms/InstCombine/rem.ll b/llvm/test/Transforms/InstCombine/rem.ll index 00c020fdae8..86a3580189f 100644 --- a/llvm/test/Transforms/InstCombine/rem.ll +++ b/llvm/test/Transforms/InstCombine/rem.ll @@ -586,7 +586,7 @@ define i32 @test22(i32 %A) { define <2 x i32> @test23(<2 x i32> %A) { ; CHECK-LABEL: @test23( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647> -; CHECK-NEXT: [[MUL:%.*]] = srem <2 x i32> [[AND]], <i32 2147483647, i32 2147483647> +; CHECK-NEXT: [[MUL:%.*]] = urem <2 x i32> [[AND]], <i32 2147483647, i32 2147483647> ; CHECK-NEXT: ret <2 x i32> [[MUL]] ; %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647> |
