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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-10-30 17:24:40 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-10-30 17:24:40 +0000 |
| commit | 194693e996f98a52a37e957e3ef59e7b4078fa89 (patch) | |
| tree | 97a76b2c6941519f545ef92291a18fb536df5ab4 | |
| parent | ad62cbe5d9dda4649c7e6edf47a53f2a0857d025 (diff) | |
| download | bcm5719-llvm-194693e996f98a52a37e957e3ef59e7b4078fa89.tar.gz bcm5719-llvm-194693e996f98a52a37e957e3ef59e7b4078fa89.zip | |
[MC] Split out register def/use idx calls to make debugging simpler. NFCI.
llvm-svn: 316927
| -rw-r--r-- | llvm/lib/CodeGen/MachineCombiner.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp index 3ffef682334..9fc990f5c24 100644 --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -161,9 +161,10 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs, assert(DefInstr && "There must be a definition for a new virtual register"); DepthOp = InstrDepth[II->second]; - LatencyOp = TSchedModel.computeOperandLatency( - DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), - InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg())); + int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); + int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg()); + LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx, + InstrPtr, UseIdx); } else { MachineInstr *DefInstr = getOperandDef(MO); if (DefInstr) { |
