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| author | Craig Topper <craig.topper@intel.com> | 2018-12-18 20:03:54 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-12-18 20:03:54 +0000 |
| commit | 18a9d545e16fecca6b7ffe039f86a55f6fb9c022 (patch) | |
| tree | ecfa6351b8fc979620d7292f72594b47d41983c1 | |
| parent | 20853a7807790a6b5ca13aab1edb0b4e96199915 (diff) | |
| download | bcm5719-llvm-18a9d545e16fecca6b7ffe039f86a55f6fb9c022.tar.gz bcm5719-llvm-18a9d545e16fecca6b7ffe039f86a55f6fb9c022.zip | |
[X86] Add BSR to isUseDefConvertible.
We already had BSF here as part of __builtin_ffs improvements and I was just wondering yesterday whether we should have BSR there.
This addresses one issue from PR40090.
llvm-svn: 349531
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pr40090.ll | 24 |
2 files changed, 30 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 98c1a12c7ac..40de049bfe8 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3579,12 +3579,12 @@ static X86::CondCode isUseDefConvertible(const MachineInstr &MI) { case X86::TZCNT32rr: case X86::TZCNT32rm: case X86::TZCNT64rr: case X86::TZCNT64rm: return X86::COND_B; - case X86::BSF16rr: - case X86::BSF16rm: - case X86::BSF32rr: - case X86::BSF32rm: - case X86::BSF64rr: - case X86::BSF64rm: + case X86::BSF16rr: case X86::BSF16rm: + case X86::BSF32rr: case X86::BSF32rm: + case X86::BSF64rr: case X86::BSF64rm: + case X86::BSR16rr: case X86::BSR16rm: + case X86::BSR32rr: case X86::BSR32rm: + case X86::BSR64rr: case X86::BSR64rm: return X86::COND_E; } } diff --git a/llvm/test/CodeGen/X86/pr40090.ll b/llvm/test/CodeGen/X86/pr40090.ll new file mode 100644 index 00000000000..d1c38e4104d --- /dev/null +++ b/llvm/test/CodeGen/X86/pr40090.ll @@ -0,0 +1,24 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s + +define i64 @foo(i64 %x, i64 %y) { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: +; CHECK-NEXT: bsrq %rdi, %rax +; CHECK-NEXT: xorq $64, %rax +; CHECK-NEXT: bsrq %rsi, %rcx +; CHECK-NEXT: cmoveq %rax, %rcx +; CHECK-NEXT: movl $63, %eax +; CHECK-NEXT: subq %rcx, %rax +; CHECK-NEXT: retq + %1 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true) + %2 = xor i64 %1, 127 + %3 = tail call i64 @llvm.ctlz.i64(i64 %y, i1 true) + %4 = xor i64 %3, 63 + %5 = icmp eq i64 %y, 0 + %6 = select i1 %5, i64 %2, i64 %4 + %7 = sub nsw i64 63, %6 + ret i64 %7 +} + +declare i64 @llvm.ctlz.i64(i64, i1) |
