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| author | Michael Liao <michael.hliao@gmail.com> | 2019-07-11 23:53:30 +0000 |
|---|---|---|
| committer | Michael Liao <michael.hliao@gmail.com> | 2019-07-11 23:53:30 +0000 |
| commit | 16d3c1ac03d34f215f253d7990b7bad7ad4cdebf (patch) | |
| tree | e8b5e7e7287624552885c5f92b6da188249a5cde | |
| parent | 803b994e9a4d1077b3d2965b964682839bc5e5c7 (diff) | |
| download | bcm5719-llvm-16d3c1ac03d34f215f253d7990b7bad7ad4cdebf.tar.gz bcm5719-llvm-16d3c1ac03d34f215f253d7990b7bad7ad4cdebf.zip | |
[AMDGPU] Skip calculating callee saved registers for entry function.
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64596
llvm-svn: 365846
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir | 54 |
2 files changed, 59 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index d73f2b4abae..44647d8ba87 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -975,8 +975,10 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedVGPRs, RegScavenger *RS) const { TargetFrameLowering::determineCalleeSaves(MF, SavedVGPRs, RS); - SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); + if (MFI->isEntryFunction()) + return; + const MachineFrameInfo &FrameInfo = MF.getFrameInfo(); const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); const SIRegisterInfo *TRI = ST.getRegisterInfo(); @@ -1049,6 +1051,8 @@ void SIFrameLowering::determineCalleeSavesSGPR(MachineFunction &MF, RegScavenger *RS) const { TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); + if (MFI->isEntryFunction()) + return; const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); const SIRegisterInfo *TRI = ST.getRegisterInfo(); diff --git a/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir b/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir new file mode 100644 index 00000000000..686a617a064 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir @@ -0,0 +1,54 @@ +# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s + +# CHECK-LABEL: all_sgpr_used +# CHECK: V_CMP_LT_U32_e64 +--- | + define amdgpu_kernel void @all_sgpr_used() #0 { + ret void + } + attributes #0 = { "amdgpu-num-sgpr"="8" "frame-pointer"="all"} +... +--- +name: all_sgpr_used +tracksRegLiveness: true +liveins: + - { reg: '$vgpr0' } + - { reg: '$vgpr1' } + - { reg: '$vgpr2' } + - { reg: '$sgpr4_sgpr5' } + - { reg: '$sgpr6_sgpr7' } + - { reg: '$sgpr8' } + - { reg: '$sgpr9' } +machineFunctionInfo: + explicitKernArgSize: 84 + maxKernArgAlign: 8 + ldsSize: 20496 + isEntryFunction: true + waveLimiter: true + scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' + scratchWaveOffsetReg: '$sgpr101' + frameOffsetReg: '$sgpr101' + stackPtrOffsetReg: '$sgpr32' + argumentInfo: + privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } + dispatchPtr: { reg: '$sgpr4_sgpr5' } + kernargSegmentPtr: { reg: '$sgpr6_sgpr7' } + workGroupIDX: { reg: '$sgpr8' } + workGroupIDY: { reg: '$sgpr9' } + privateSegmentWaveByteOffset: { reg: '$sgpr10' } + workItemIDX: { reg: '$vgpr0' } + workItemIDY: { reg: '$vgpr1' } + workItemIDZ: { reg: '$vgpr2' } +body: | + bb.0: + liveins: $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7 + $sgpr0 = S_MOV_B32 0 + $sgpr1 = S_MOV_B32 0 + $sgpr2 = S_MOV_B32 0 + $sgpr3 = S_MOV_B32 0 + $sgpr4 = S_MOV_B32 0 + $sgpr5 = S_MOV_B32 0 + $sgpr6 = S_MOV_B32 0 + $sgpr7 = S_MOV_B32 0 + $vcc = V_CMP_LT_U32_e64 $sgpr8, $vgpr1, implicit $exec +... |
