diff options
| author | Craig Topper <craig.topper@intel.com> | 2019-08-30 00:54:36 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-08-30 00:54:36 +0000 |
| commit | 160ed4cab4e1f25f2d6668d691577abab651f2d8 (patch) | |
| tree | 30b79fc0e837026ba903f45db7017446019e9668 | |
| parent | be638099a476840596d8df3c1361b8ed1fb45ec4 (diff) | |
| download | bcm5719-llvm-160ed4cab4e1f25f2d6668d691577abab651f2d8.tar.gz bcm5719-llvm-160ed4cab4e1f25f2d6668d691577abab651f2d8.zip | |
[X86] Explicitly list all the always trivially rematerializable instructions.
Add a default with an llvm_unreachable for anything we don't expect.
This seems safer that just blindly returning true for anything
missing from the switch.
llvm-svn: 370424
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 45 |
1 files changed, 40 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 3077288b794..d3e0a888ff5 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -482,7 +482,46 @@ static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const { switch (MI.getOpcode()) { - default: break; + default: + // This function should only be called for opcodes with the ReMaterializable + // flag set. + llvm_unreachable("Unknown rematerializable operation!"); + break; + + case X86::LOAD_STACK_GUARD: + case X86::AVX1_SETALLONES: + case X86::AVX2_SETALLONES: + case X86::AVX512_128_SET0: + case X86::AVX512_256_SET0: + case X86::AVX512_512_SET0: + case X86::AVX512_512_SETALLONES: + case X86::AVX512_FsFLD0SD: + case X86::AVX512_FsFLD0SS: + case X86::AVX_SET0: + case X86::FsFLD0SD: + case X86::FsFLD0SS: + case X86::KSET0D: + case X86::KSET0Q: + case X86::KSET0W: + case X86::KSET1D: + case X86::KSET1Q: + case X86::KSET1W: + case X86::MMX_SET0: + case X86::MOV32ImmSExti8: + case X86::MOV32r0: + case X86::MOV32r1: + case X86::MOV32r_1: + case X86::MOV32ri64: + case X86::MOV64ImmSExti8: + case X86::V_SET0: + case X86::V_SETALLONES: + case X86::MOV16ri: + case X86::MOV32ri: + case X86::MOV64ri: + case X86::MOV64ri32: + case X86::MOV8ri: + return true; + case X86::MOV8rm: case X86::MOV8rm_NOREX: case X86::MOV16rm: @@ -594,10 +633,6 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, return false; } } - - // All other instructions marked M_REMATERIALIZABLE are always trivially - // rematerializable. - return true; } void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, |
