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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2017-12-11 14:46:06 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2017-12-11 14:46:06 +0000
commit152414595ba0ef29b157619f727720214e2a43db (patch)
tree97c94ee65ea27d093e6536308f3527115395dcaf
parent50d37a112974e32f19049fd07964c498bf9a29c3 (diff)
downloadbcm5719-llvm-152414595ba0ef29b157619f727720214e2a43db.tar.gz
bcm5719-llvm-152414595ba0ef29b157619f727720214e2a43db.zip
[Hexagon] Crash in instruction selection for insert_vector_elt for HVX
A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. llvm-svn: 320369
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp2
-rw-r--r--llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll23
2 files changed, 24 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index de2ac42ad51..c397ddcd3bc 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -280,7 +280,7 @@ HexagonTargetLowering::LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG)
SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG);
MVT SubVecTy = tyVector(ty(Ext), ElemTy);
SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext),
- ValV, SubIdx, dl, SubVecTy, DAG);
+ ValV, SubIdx, dl, ElemTy, DAG);
// 3. Insert the 32-bit word back into the original vector.
return InsertWord(VecV, Ins, ByteIdx);
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll b/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
new file mode 100644
index 00000000000..22afa4a3c1f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
@@ -0,0 +1,23 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; REQUIRES: asserts
+
+; Check that this testcase compiles successfully.
+; CHECK: vextract
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon-unknown--elf"
+
+define void @fred() local_unnamed_addr #0 {
+b0:
+ %v1 = load <64 x i8>, <64 x i8>* undef, align 64
+ %v2 = insertelement <64 x i8> %v1, i8 0, i32 0
+ br label %b3
+
+b3: ; preds = %b3, %b0
+ %v4 = phi <64 x i8> [ %v2, %b0 ], [ %v6, %b3 ]
+ %v5 = extractelement <64 x i8> %v4, i32 0
+ %v6 = insertelement <64 x i8> %v4, i8 undef, i32 0
+ br label %b3
+}
+
+attributes #0 = { "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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