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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-01-24 21:19:51 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-01-24 21:19:51 +0000 |
| commit | 14f3ef1f0ed0d6b835306afd5eead5177e2d9002 (patch) | |
| tree | 2c1d027a804da125bb225b76f698706ecdfd4de2 | |
| parent | a396df34725fcbb03a96ba196b58eb2244447df7 (diff) | |
| download | bcm5719-llvm-14f3ef1f0ed0d6b835306afd5eead5177e2d9002.tar.gz bcm5719-llvm-14f3ef1f0ed0d6b835306afd5eead5177e2d9002.zip | |
[Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing code
The code in EmitFunctionEntryCode needs to know the maximum stack
alignment, but it runs very early in the selection process (before
lowering). The final stack alignment may change during lowering, so
the code needs to be moved to where the alignment is known.
llvm-svn: 323374
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 35 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h | 3 |
2 files changed, 22 insertions, 16 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index eb8fab13626..09c55cb2618 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1034,6 +1034,23 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) { } } +void HexagonDAGToDAGISel::ppEmitAligna() { + auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget()); + auto &HFI = *HST.getFrameLowering(); + if (!HFI.needsAligna(*MF)) + return; + + MachineFrameInfo &MFI = MF->getFrameInfo(); + MachineBasicBlock &EntryBB = MF->front(); + unsigned AR = FuncInfo->CreateReg(MVT::i32); + unsigned MaxA = MFI.getMaxAlignment(); + MachineBasicBlock::iterator End = EntryBB.end(); + DebugLoc DL = EntryBB.findDebugLoc(End); + BuildMI(EntryBB, End, DL, HII->get(Hexagon::PS_aligna), AR) + .addImm(MaxA); + MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR); +} + void HexagonDAGToDAGISel::PreprocessISelDAG() { // Repack all nodes before calling each preprocessing function, // because each of them can modify the set of nodes. @@ -1089,21 +1106,11 @@ void HexagonDAGToDAGISel::PreprocessISelDAG() { CurDAG->dump(); }); } -} - -void HexagonDAGToDAGISel::EmitFunctionEntryCode() { - auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget()); - auto &HFI = *HST.getFrameLowering(); - if (!HFI.needsAligna(*MF)) - return; - MachineFrameInfo &MFI = MF->getFrameInfo(); - MachineBasicBlock *EntryBB = &MF->front(); - unsigned AR = FuncInfo->CreateReg(MVT::i32); - unsigned MaxA = MFI.getMaxAlignment(); - BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR) - .addImm(MaxA); - MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR); + // Finally, emit the PS_aligna instruction, if necessary. Do it late, + // because the max required stack layout may change up until right before + // instruction selection. + ppEmitAligna(); } // Match a frame index that can be used in an addressing mode. diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h index dd2c6f4fc95..c80d375aa7b 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -51,8 +51,6 @@ public: return true; } void PreprocessISelDAG() override; - void EmitFunctionEntryCode() override; - void Select(SDNode *N) override; // Complex Pattern Selectors. @@ -139,6 +137,7 @@ private: void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes); void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes); void ppHoistZextI1(std::vector<SDNode*> &&Nodes); + void ppEmitAligna(); SmallDenseMap<SDNode *,int> RootWeights; SmallDenseMap<SDNode *,int> RootHeights; |

