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| author | Yaxun Liu <Yaxun.Liu@amd.com> | 2017-03-25 02:05:44 +0000 |
|---|---|---|
| committer | Yaxun Liu <Yaxun.Liu@amd.com> | 2017-03-25 02:05:44 +0000 |
| commit | 14834c3e3de8caea7876648e41464952b4d81b42 (patch) | |
| tree | bf02430645a2225fa42dda861d30c8dd9b661829 | |
| parent | 72b8acfb70df521a501f8731489e5e0ec094dd99 (diff) | |
| download | bcm5719-llvm-14834c3e3de8caea7876648e41464952b4d81b42.tar.gz bcm5719-llvm-14834c3e3de8caea7876648e41464952b4d81b42.zip | |
[AMDGPU] Switch data layout by triple environment amdgiz
Switch data layout by target triple environment amdgiz and amdgizcl indicating using of an address space mapping in which generic address space is 0.
amdgiz is for non-OpenCL environment where generic address space is 0.
amdgizcl is for OpenCL environment where generic address space is 0.
Differential Revision: https://reviews.llvm.org/D31211
llvm-svn: 298758
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/env-amdgiz.ll | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/env-amdgizcl.ll | 11 |
3 files changed, 28 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 46e458a2e38..68e78d50ef0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -203,9 +203,14 @@ static StringRef computeDataLayout(const Triple &TT) { // 32-bit private, local, and region pointers. 64-bit global, constant and // flat. - return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" + if (TT.getEnvironmentName() == "amdgiz" || + TT.getEnvironmentName() == "amdgizcl") + return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; + return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" + "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" + "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; } LLVM_READNONE diff --git a/llvm/test/CodeGen/AMDGPU/env-amdgiz.ll b/llvm/test/CodeGen/AMDGPU/env-amdgiz.ll new file mode 100644 index 00000000000..10b51428882 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/env-amdgiz.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgiz -verify-machineinstrs < %s +; Just check the target feature and data layout is accepted without error. + +target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" +target triple = "amdgcn-amd-amdhsa-amdgiz" + +define void @foo() { +entry: + ret void +} + diff --git a/llvm/test/CodeGen/AMDGPU/env-amdgizcl.ll b/llvm/test/CodeGen/AMDGPU/env-amdgizcl.ll new file mode 100644 index 00000000000..5f463afeaa1 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/env-amdgizcl.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgizcl -verify-machineinstrs < %s +; Just check the target feature and data layout is accepted without error. + +target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" +target triple = "amdgcn-amd-amdhsa-amdgizcl" + +define void @foo() { +entry: + ret void +} + |
