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| author | Ayman Musa <ayman.musa@intel.com> | 2017-04-26 11:34:09 +0000 |
|---|---|---|
| committer | Ayman Musa <ayman.musa@intel.com> | 2017-04-26 11:34:09 +0000 |
| commit | 11966ab00b46fd3e7d1b46a9708bc266f0f96c35 (patch) | |
| tree | c53fcecf648ac3ce371c15b3f460a7a576535d77 | |
| parent | 70f79251bc7a9c50b9601a6b223241a2b79cd461 (diff) | |
| download | bcm5719-llvm-11966ab00b46fd3e7d1b46a9708bc266f0f96c35.tar.gz bcm5719-llvm-11966ab00b46fd3e7d1b46a9708bc266f0f96c35.zip | |
[X86] Add missing mayLoad/mayStore attributes to some X86 instructions (Continue)
Complete the patch committed in rL300190.
Differential Revision: https://reviews.llvm.org/D32287
llvm-svn: 301393
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrArithmetic.td | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index bfd21c062aa..66382014f6e 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -989,10 +989,12 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, } } // Constraints = "$src1 = $dst" - def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>; - def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>; - def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>; - def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>; + let mayLoad = 1, mayStore = 1 in { + def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>; + def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>; + def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>; + def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>; + } // NOTE: These are order specific, we want the mi8 forms to be listed // first so that they are slightly preferred to the mi forms. |
