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authorCraig Topper <craig.topper@intel.com>2019-01-05 23:30:28 +0000
committerCraig Topper <craig.topper@intel.com>2019-01-05 23:30:28 +0000
commit1187991bcf64eaa5616860b28fc9eb08711e8bd6 (patch)
treed0737143a7cd82aff74b64f80f89880d06cf538a
parentb25ced7480847210561fb03c2e926ea3e2c6f204 (diff)
downloadbcm5719-llvm-1187991bcf64eaa5616860b28fc9eb08711e8bd6.tar.gz
bcm5719-llvm-1187991bcf64eaa5616860b28fc9eb08711e8bd6.zip
[X86][AsmParser] Don't allow X86::DX in CheckBaseRegAndIndexRegAndScale.
This was here because out and in instructions allow '(%dx)' even though its not a memory reference. To handle this we build a special operand for the DX register reference before we get to the call to CheckBaseRegAndIndexRegAndScale. So we no longer need this special case. llvm-svn: 350483
-rw-r--r--llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 4801078925c..8f7b24f89bf 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1011,8 +1011,7 @@ static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
// and then only in non-64-bit modes.
if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
(Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
- BaseReg != X86::SI && BaseReg != X86::DI)) &&
- BaseReg != X86::DX) {
+ BaseReg != X86::SI && BaseReg != X86::DI))) {
ErrMsg = "invalid 16-bit base register";
return true;
}
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