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authorTim Northover <tnorthover@apple.com>2017-04-21 17:21:59 +0000
committerTim Northover <tnorthover@apple.com>2017-04-21 17:21:59 +0000
commit1061ccca8c9214e9ea1de9dd85a7897d700c1478 (patch)
tree97657bc5d1b784e3524f2394c57eb28dbc2e443b
parent676d008198f7f7809ffe03fe6d72f406d7f6a3aa (diff)
downloadbcm5719-llvm-1061ccca8c9214e9ea1de9dd85a7897d700c1478.tar.gz
bcm5719-llvm-1061ccca8c9214e9ea1de9dd85a7897d700c1478.zip
ARM: don't try to create an i8 -> i32 vpaddl.
DAG combine was mistakenly assuming that the step-up it was looking at was always a doubling, but it can sometimes be a larger extension in which case we'd crash. llvm-svn: 301002
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp7
-rw-r--r--llvm/test/CodeGen/ARM/vpadd.ll11
2 files changed, 16 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 0f8cdad983d..df840d723e3 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -9480,8 +9480,11 @@ AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1,
return SDValue();
}
- // Don't generate vpaddl+vmovn; we'll match it to vpadd later.
- if (Vec.getValueType().getVectorElementType() == VT.getVectorElementType())
+ // Don't generate vpaddl+vmovn; we'll match it to vpadd later. Also don't try
+ // to handle an i8 -> i32 situation (or similar). vpaddl can only double the
+ // size.
+ if (2 * Vec.getValueType().getVectorElementType().getSizeInBits() !=
+ VT.getVectorElementType().getSizeInBits())
return SDValue();
// Create VPADDL node.
diff --git a/llvm/test/CodeGen/ARM/vpadd.ll b/llvm/test/CodeGen/ARM/vpadd.ll
index 1aa23597cf4..9720f801029 100644
--- a/llvm/test/CodeGen/ARM/vpadd.ll
+++ b/llvm/test/CodeGen/ARM/vpadd.ll
@@ -485,6 +485,17 @@ define <2 x i16> @fromExtendingExtractVectorElt_i16(<4 x i16> %in) {
ret <2 x i16> %x
}
+; And <2 x i8> to <2 x i32>
+define <2 x i8> @fromExtendingExtractVectorElt_2i8(<8 x i8> %in) {
+; CHECK-LABEL: fromExtendingExtractVectorElt_2i8:
+; CHECK: vadd.i32
+ %tmp1 = shufflevector <8 x i8> %in, <8 x i8> undef, <2 x i32> <i32 0, i32 2>
+ %tmp2 = shufflevector <8 x i8> %in, <8 x i8> undef, <2 x i32> <i32 1, i32 3>
+ %x = add <2 x i8> %tmp2, %tmp1
+ ret <2 x i8> %x
+}
+
+
declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone
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