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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2015-09-04 19:47:56 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2015-09-04 19:47:56 +0000 |
| commit | 0fccef6ac2fc87f4dd29a1d098723cd2869a09ab (patch) | |
| tree | 1c374b1f4b679f48f9edd655727e4535c26f1cf8 | |
| parent | 07dcb58f8a2b01514e3b8d2329ce08ac9342e098 (diff) | |
| download | bcm5719-llvm-0fccef6ac2fc87f4dd29a1d098723cd2869a09ab.tar.gz bcm5719-llvm-0fccef6ac2fc87f4dd29a1d098723cd2869a09ab.zip | |
[X86][AVX] Test tidyup + regeneration. NFCI.
llvm-svn: 246863
| -rw-r--r-- | llvm/test/CodeGen/X86/avx-shuffle-x86_32.ll | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/X86/avx-shuffle-x86_32.ll b/llvm/test/CodeGen/X86/avx-shuffle-x86_32.ll index 4bdba37c711..a24bd46af41 100644 --- a/llvm/test/CodeGen/X86/avx-shuffle-x86_32.ll +++ b/llvm/test/CodeGen/X86/avx-shuffle-x86_32.ll @@ -1,19 +1,25 @@ -; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s +; Avoid unnecessary vinsertf128 define <4 x i64> @test1(<4 x i64> %a) nounwind { +; CHECK-LABEL: test1: +; CHECK: # BB#0: +; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 +; CHECK-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] +; CHECK-NEXT: retl %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> ret <4 x i64>%b - ; CHECK-LABEL: test1: - ; CHECK-NOT: vinsertf128 - } +} define <8 x i16> @test2(<4 x i16>* %v) nounwind { -; CHECK-LABEL: test2 -; CHECK: vmovsd -; CHECK: vmovq +; CHECK-LABEL: test2: +; CHECK: # BB#0: +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero +; CHECK-NEXT: retl %v9 = load <4 x i16>, <4 x i16> * %v, align 8 %v10 = shufflevector <4 x i16> %v9, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %v11 = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %v10, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %v11 } - |
