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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-05 20:32:25 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-05 20:32:25 +0000 |
| commit | 0f8a764e8fa831c037f07c109aea947ec4a1e4f5 (patch) | |
| tree | 7d1a6fbf0507bf3db59438802d08ec6a9aace901 | |
| parent | ecf3ae4a7032d2a5ee42433d4e5d002ac349adbf (diff) | |
| download | bcm5719-llvm-0f8a764e8fa831c037f07c109aea947ec4a1e4f5.tar.gz bcm5719-llvm-0f8a764e8fa831c037f07c109aea947ec4a1e4f5.zip | |
AMDGPU: Fix using 2 different enums for same operand flags
These enums are really for the same namespace of flags set on
arbitrary MachineOperands, so merge them to avoid value collisions.
llvm-svn: 362640
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.h | 11 |
3 files changed, 8 insertions, 11 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp index ce19f2559ef..017d4ad1625 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -112,10 +112,10 @@ const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr( const MCConstantExpr *One = MCConstantExpr::create(4, Ctx); SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx); - if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD) + if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD) return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx); - assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD); + assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD); return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx); } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index c25be611cb7..1c3c52ba02c 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1532,7 +1532,7 @@ unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32)) .addReg(PCReg, RegState::Define, AMDGPU::sub0) .addReg(PCReg, 0, AMDGPU::sub0) - .addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_FORWARD); + .addMBB(&DestBB, MO_LONG_BRANCH_FORWARD); BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32)) .addReg(PCReg, RegState::Define, AMDGPU::sub1) .addReg(PCReg, 0, AMDGPU::sub1) @@ -1542,7 +1542,7 @@ unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32)) .addReg(PCReg, RegState::Define, AMDGPU::sub0) .addReg(PCReg, 0, AMDGPU::sub0) - .addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_BACKWARD); + .addMBB(&DestBB, MO_LONG_BRANCH_BACKWARD); BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32)) .addReg(PCReg, RegState::Define, AMDGPU::sub1) .addReg(PCReg, 0, AMDGPU::sub1) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index c4038b3dc29..3dfb4deb0fe 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -157,7 +157,10 @@ public: MO_REL32 = 4, MO_REL32_LO = 4, // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI. - MO_REL32_HI = 5 + MO_REL32_HI = 5, + + MO_LONG_BRANCH_FORWARD = 6, + MO_LONG_BRANCH_BACKWARD = 7 }; explicit SIInstrInfo(const GCNSubtarget &ST); @@ -1030,12 +1033,6 @@ namespace AMDGPU { const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21); const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23); - // For MachineOperands. - enum TargetFlags { - TF_LONG_BRANCH_FORWARD = 1 << 0, - TF_LONG_BRANCH_BACKWARD = 1 << 1 - }; - } // end namespace AMDGPU namespace SI { |
