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| author | Craig Topper <craig.topper@intel.com> | 2018-01-06 21:02:26 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-06 21:02:26 +0000 |
| commit | 0f4ccb78067578e1666bbd9ea86b417a892ee571 (patch) | |
| tree | b02120bf58911277a1531720125770c311d6d6cc | |
| parent | 90353a9f42a3c99c34cbdaf7d6ea1ab47badccd2 (diff) | |
| download | bcm5719-llvm-0f4ccb78067578e1666bbd9ea86b417a892ee571.tar.gz bcm5719-llvm-0f4ccb78067578e1666bbd9ea86b417a892ee571.zip | |
[X86] Add load folding pattern to EVEX vcvttss2si/vcvtsd2si.
llvm-svn: 321945
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 13 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-intrinsics.ll | 10 |
2 files changed, 17 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 3c06ca34fa0..a701471c1af 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6616,12 +6616,13 @@ let Predicates = [HasAVX512] in { [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src), (i32 FROUND_NO_EXC)))], itins.rr>, EVEX,VEX_LIG , EVEX_B, Sched<[itins.Sched]>; - let mayLoad = 1, hasSideEffects = 0 in - def rm_Int : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), - (ins _SrcRC.IntScalarMemOp:$src), - !strconcat(asm,"\t{$src, $dst|$dst, $src}"), - [], itins.rm>, EVEX, VEX_LIG, - Sched<[itins.Sched.Folded, ReadAfterLd]>; + def rm_Int : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), + (ins _SrcRC.IntScalarMemOp:$src), + !strconcat(asm,"\t{$src, $dst|$dst, $src}"), + [(set _DstRC.RC:$dst, (OpNodeRnd + (_SrcRC.VT _SrcRC.ScalarIntMemCPat:$src), + (i32 FROUND_CURRENT)))], itins.rm>, + EVEX, VEX_LIG, Sched<[itins.Sched.Folded, ReadAfterLd]>; def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}", (!cast<Instruction>(NAME # "rr_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0>; diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics.ll b/llvm/test/CodeGen/X86/avx512-intrinsics.ll index 5faa202c30f..5069b727eda 100644 --- a/llvm/test/CodeGen/X86/avx512-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512-intrinsics.ll @@ -503,6 +503,16 @@ define i32 @test_x86_avx512_cvttss2si(<4 x float> %a0) { } declare i32 @llvm.x86.avx512.cvttss2si(<4 x float>, i32) nounwind readnone +define i32 @test_x86_avx512_cvttss2si_load(<4 x float>* %a0) { +; CHECK-LABEL: test_x86_avx512_cvttss2si_load: +; CHECK: ## %bb.0: +; CHECK-NEXT: vcvttss2si (%rdi), %eax +; CHECK-NEXT: retq + %a1 = load <4 x float>, <4 x float>* %a0 + %res = call i32 @llvm.x86.avx512.cvttss2si(<4 x float> %a1, i32 4) ; + ret i32 %res +} + define i64 @test_x86_avx512_cvttss2si64(<4 x float> %a0) { ; CHECK-LABEL: test_x86_avx512_cvttss2si64: ; CHECK: ## %bb.0: |
