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author | Craig Topper <craig.topper@gmail.com> | 2015-01-06 04:23:57 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2015-01-06 04:23:57 +0000 |
commit | 0f2c4ac6497329a19b877d56be15c9cebbeaf026 (patch) | |
tree | 7666d023dba9090eb41438dfd72dd468b0e6a322 | |
parent | 49758aab94b2e64543cabb6e6ed84c434d11b96e (diff) | |
download | bcm5719-llvm-0f2c4ac6497329a19b877d56be15c9cebbeaf026.tar.gz bcm5719-llvm-0f2c4ac6497329a19b877d56be15c9cebbeaf026.zip |
[X86] Remove 16-bit and 32-bit offset jump instructions from the AsmParser. We always select the 8-bit size and let the assembler backend relax to the larger size.
llvm-svn: 225243
-rw-r--r-- | llvm/lib/Target/X86/X86InstrControl.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td index 48c9897cd03..5dbddef0bd6 100644 --- a/llvm/lib/Target/X86/X86InstrControl.td +++ b/llvm/lib/Target/X86/X86InstrControl.td @@ -59,7 +59,7 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>; - let hasSideEffects = 0 in { + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst), "jmp\t$dst", [], IIC_JMP_REL>, OpSize16; def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst), @@ -72,7 +72,7 @@ let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>; - let hasSideEffects = 0 in { + let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm, [], IIC_Jcc>, OpSize16, TB; def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm, |