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| author | Amaury Sechet <deadalnix@gmail.com> | 2018-05-06 16:00:23 +0000 |
|---|---|---|
| committer | Amaury Sechet <deadalnix@gmail.com> | 2018-05-06 16:00:23 +0000 |
| commit | 0ea293610458af599c470afdab3a58cc20281bc7 (patch) | |
| tree | 6029de98d93384cf20c6110026d91d644b20afa6 | |
| parent | acc008cb0c677b07dac93a28ab560b9fcb7297b4 (diff) | |
| download | bcm5719-llvm-0ea293610458af599c470afdab3a58cc20281bc7.tar.gz bcm5719-llvm-0ea293610458af599c470afdab3a58cc20281bc7.zip | |
Add test cases for large integer legalization of add and sub. NFC
llvm-svn: 331604
| -rw-r--r-- | llvm/test/CodeGen/X86/addcarry.ll | 31 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/subcarry.ll | 31 |
2 files changed, 62 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll index 7bd0b9db5b7..e07727edd10 100644 --- a/llvm/test/CodeGen/X86/addcarry.ll +++ b/llvm/test/CodeGen/X86/addcarry.ll @@ -1,6 +1,37 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s +define i128 @add128(i128 %a, i128 %b) nounwind { +; CHECK-LABEL: add128: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq %rdx, %rdi +; CHECK-NEXT: adcq %rcx, %rsi +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: movq %rsi, %rdx +; CHECK-NEXT: retq +entry: + %0 = add i128 %a, %b + ret i128 %0 +} + +define i256 @add256(i256 %a, i256 %b) nounwind { +; CHECK-LABEL: add256: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq %r9, %rsi +; CHECK-NEXT: adcq {{[0-9]+}}(%rsp), %rdx +; CHECK-NEXT: adcq {{[0-9]+}}(%rsp), %rcx +; CHECK-NEXT: adcq {{[0-9]+}}(%rsp), %r8 +; CHECK-NEXT: movq %rdx, 8(%rdi) +; CHECK-NEXT: movq %rsi, (%rdi) +; CHECK-NEXT: movq %rcx, 16(%rdi) +; CHECK-NEXT: movq %r8, 24(%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq +entry: + %0 = add i256 %a, %b + ret i256 %0 +} + define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind { ; CHECK-LABEL: a: ; CHECK: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/X86/subcarry.ll b/llvm/test/CodeGen/X86/subcarry.ll index 862d489e138..90d4caa0446 100644 --- a/llvm/test/CodeGen/X86/subcarry.ll +++ b/llvm/test/CodeGen/X86/subcarry.ll @@ -1,6 +1,37 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s +define i128 @sub128(i128 %a, i128 %b) nounwind { +; CHECK-LABEL: sub128: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subq %rdx, %rdi +; CHECK-NEXT: sbbq %rcx, %rsi +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: movq %rsi, %rdx +; CHECK-NEXT: retq +entry: + %0 = sub i128 %a, %b + ret i128 %0 +} + +define i256 @sub256(i256 %a, i256 %b) nounwind { +; CHECK-LABEL: sub256: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subq %r9, %rsi +; CHECK-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx +; CHECK-NEXT: sbbq {{[0-9]+}}(%rsp), %rcx +; CHECK-NEXT: sbbq {{[0-9]+}}(%rsp), %r8 +; CHECK-NEXT: movq %rdx, 8(%rdi) +; CHECK-NEXT: movq %rsi, (%rdi) +; CHECK-NEXT: movq %rcx, 16(%rdi) +; CHECK-NEXT: movq %r8, 24(%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq +entry: + %0 = sub i256 %a, %b + ret i256 %0 +} + %S = type { [4 x i64] } define %S @negate(%S* nocapture readonly %this) { |
