summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAdrian Prantl <aprantl@apple.com>2015-01-12 22:37:16 +0000
committerAdrian Prantl <aprantl@apple.com>2015-01-12 22:37:16 +0000
commit0e6ffb9d0d0f4ca27a9e4bfdcf00ca57c681a2fa (patch)
tree8e6a5811c844d340890a491ab0a5a7c5a2847a22
parent49503f827ddfba6c741ba60bb86cda942c92d672 (diff)
downloadbcm5719-llvm-0e6ffb9d0d0f4ca27a9e4bfdcf00ca57c681a2fa.tar.gz
bcm5719-llvm-0e6ffb9d0d0f4ca27a9e4bfdcf00ca57c681a2fa.zip
Debug Info: Implement DwarfUnit::addRegisterOpPiece() using DwarfExpression.
NFC. llvm-svn: 225717
-rw-r--r--llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp3
-rw-r--r--llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp58
2 files changed, 4 insertions, 57 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
index 2b6911e32e8..e398e46b323 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -90,7 +90,8 @@ void DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
// If this is a valid register number, emit it.
if (Reg >= 0) {
AddReg(Reg);
- AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
+ if (PieceSizeInBits)
+ AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
return;
}
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
index 16cdbbc7e7e..89987953580 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
@@ -429,64 +429,10 @@ void DwarfUnit::addSourceLine(DIE &Die, DINameSpace NS) {
}
/// addRegisterOp - Add register operand.
-// FIXME: Ideally, this would share the implementation with
-// AsmPrinter::EmitDwarfRegOpPiece.
bool DwarfUnit::addRegisterOpPiece(DIELoc &TheDie, unsigned Reg,
unsigned SizeInBits, unsigned OffsetInBits) {
- const TargetRegisterInfo *RI = Asm->TM.getSubtargetImpl()->getRegisterInfo();
- int DWReg = RI->getDwarfRegNum(Reg, false);
- bool isSubRegister = DWReg < 0;
-
- unsigned Idx = 0;
-
- // Go up the super-register chain until we hit a valid dwarf register number.
- for (MCSuperRegIterator SR(Reg, RI); SR.isValid() && DWReg < 0; ++SR) {
- DWReg = RI->getDwarfRegNum(*SR, false);
- if (DWReg >= 0)
- Idx = RI->getSubRegIndex(*SR, Reg);
- }
-
- if (DWReg < 0)
- return false;
-
- // Emit register.
- if (DWReg < 32)
- addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + DWReg);
- else {
- addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_regx);
- addUInt(TheDie, dwarf::DW_FORM_udata, DWReg);
- }
-
- // Emit mask.
- bool isPiece = SizeInBits > 0;
- if (isSubRegister || isPiece) {
- const unsigned SizeOfByte = 8;
- unsigned RegSizeInBits = RI->getSubRegIdxSize(Idx);
- unsigned RegOffsetInBits = RI->getSubRegIdxOffset(Idx);
- unsigned PieceSizeInBits = std::max(SizeInBits, RegSizeInBits);
- unsigned PieceOffsetInBits = OffsetInBits ? OffsetInBits : RegOffsetInBits;
- assert(RegSizeInBits >= SizeInBits && "register smaller than value");
-
- if (RegOffsetInBits != PieceOffsetInBits) {
- // Manually shift the value into place, since the DW_OP_piece
- // describes the part of the variable, not the position of the
- // subregister.
- addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_constu);
- addUInt(TheDie, dwarf::DW_FORM_data1, RegOffsetInBits);
- addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_shr);
- }
-
- if (PieceOffsetInBits > 0 || PieceSizeInBits % SizeOfByte) {
- assert(PieceSizeInBits > 0 && "piece has zero size");
- addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_bit_piece);
- addUInt(TheDie, dwarf::DW_FORM_data1, PieceSizeInBits);
- addUInt(TheDie, dwarf::DW_FORM_data1, PieceOffsetInBits);
- } else {
- assert(PieceSizeInBits > 0 && "piece has zero size");
- addUInt(TheDie, dwarf::DW_FORM_data1, dwarf::DW_OP_piece);
- addUInt(TheDie, dwarf::DW_FORM_data1, PieceSizeInBits/SizeOfByte);
- }
- }
+ DIEDwarfExpression Expr(Asm->TM, *this, TheDie);
+ Expr.AddMachineRegPiece(Reg, SizeInBits, OffsetInBits);
return true;
}
OpenPOWER on IntegriCloud