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authorSanjoy Das <sanjoy@playingwithpointers.com>2018-04-26 20:52:27 +0000
committerSanjoy Das <sanjoy@playingwithpointers.com>2018-04-26 20:52:27 +0000
commit0e643db48ff92b36c19582e544a8e21b3f5c11ca (patch)
treede4756117303a4948a12f118e6479a5a657db942
parent824eb0e6a0585e647e20fdc4314b251cffdc241f (diff)
downloadbcm5719-llvm-0e643db48ff92b36c19582e544a8e21b3f5c11ca.tar.gz
bcm5719-llvm-0e643db48ff92b36c19582e544a8e21b3f5c11ca.zip
Add test cases to prepare for the optimization that simplifies Add with
remainder expressions as operands. Summary: Add test cases to prepare for the new optimization that Simplifies integer add expression X % C0 + (( X / C0 ) % C1) * C0 to X % (C0 * C1). Patch by Bixia Zheng! Reviewers: sanjoy Reviewed By: sanjoy Subscribers: jlebar, llvm-commits Differential Revision: https://reviews.llvm.org/D46017 llvm-svn: 330991
-rw-r--r--llvm/test/Transforms/InstCombine/add4.ll78
1 files changed, 78 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/add4.ll b/llvm/test/Transforms/InstCombine/add4.ll
new file mode 100644
index 00000000000..60fb86b0129
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/add4.ll
@@ -0,0 +1,78 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+; ModuleID = 'test/Transforms/InstCombine/add4.ll'
+source_filename = "test/Transforms/InstCombine/add4.ll"
+
+define i64 @match_unsigned(i64 %x) {
+; CHECK-LABEL: @match_unsigned(
+; CHECK: [[TMP:%.*]] = add
+; CHECK-NEXT: ret i64 [[TMP]]
+;
+bb:
+ %tmp = urem i64 %x, 299
+ %tmp1 = udiv i64 %x, 299
+ %tmp2 = urem i64 %tmp1, 64
+ %tmp3 = mul i64 %tmp2, 299
+ %tmp4 = add nuw nsw i64 %tmp, %tmp3
+ ret i64 %tmp4
+}
+
+define i64 @match_andAsRem_lshrAsDiv_shlAsMul(i64 %x) {
+; CHECK-LABEL: @match_andAsRem_lshrAsDiv_shlAsMul(
+; CHECK: [[TMP:%.*]] = or
+; CHECK-NEXT: ret i64 [[TMP]]
+;
+bb:
+ %tmp = and i64 %x, 63
+ %tmp1 = lshr i64 %x, 6
+ %tmp2 = urem i64 %tmp1, 9
+ %tmp3 = shl nuw nsw i64 %tmp2, 6
+ %tmp4 = add nuw nsw i64 %tmp, %tmp3
+ ret i64 %tmp4
+}
+
+define i64 @match_signed(i64 %x) {
+; CHECK-LABEL: @match_signed(
+; CHECK: [[TMP1:%.*]] = add
+; CHECK: [[TMP2:%.*]] = add
+; CHECK-NEXT: ret i64 [[TMP2]]
+;
+bb:
+ %tmp = srem i64 %x, 299
+ %tmp1 = sdiv i64 %x, 299
+ %tmp2 = srem i64 %tmp1, 64
+ %tmp3 = sdiv i64 %x, 19136
+ %tmp4 = srem i64 %tmp3, 9
+ %tmp5 = mul nuw nsw i64 %tmp2, 299
+ %tmp6 = add nuw nsw i64 %tmp, %tmp5
+ %tmp7 = mul nuw nsw i64 %tmp4, 19136
+ %tmp8 = add nuw nsw i64 %tmp6, %tmp7
+ ret i64 %tmp8
+}
+
+define i64 @not_match_inconsistent_signs(i64 %x) {
+; CHECK-LABEL: @not_match_inconsistent_signs(
+; CHECK: [[TMP:%.*]] = add
+; CHECK-NEXT: ret i64 [[TMP]]
+;
+bb:
+ %tmp = urem i64 %x, 299
+ %tmp1 = sdiv i64 %x, 299
+ %tmp2 = urem i64 %tmp1, 64
+ %tmp3 = mul i64 %tmp2, 299
+ %tmp4 = add nuw nsw i64 %tmp, %tmp3
+ ret i64 %tmp4
+}
+
+define i64 @not_match_inconsistent_values(i64 %x) {
+; CHECK-LABEL: @not_match_inconsistent_values(
+; CHECK: [[TMP:%.*]] = add
+; CHECK-NEXT: ret i64 [[TMP]]
+;
+bb:
+ %tmp = urem i64 %x, 299
+ %tmp1 = udiv i64 %x, 29
+ %tmp2 = urem i64 %tmp1, 64
+ %tmp3 = mul i64 %tmp2, 299
+ %tmp4 = add nuw nsw i64 %tmp, %tmp3
+ ret i64 %tmp4
+}
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