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| author | Craig Topper <craig.topper@intel.com> | 2019-06-17 23:08:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-06-17 23:08:09 +0000 |
| commit | 0e18300802960b5b270b8b7801384c79b5ab16f4 (patch) | |
| tree | 40511e5cd827e52816bdeafb13c6c6e116bd3f37 | |
| parent | 36a7a98272232fbe742963cae086b3e2ec762770 (diff) | |
| download | bcm5719-llvm-0e18300802960b5b270b8b7801384c79b5ab16f4.tar.gz bcm5719-llvm-0e18300802960b5b270b8b7801384c79b5ab16f4.zip | |
[X86] Make an assert in LowerSCALAR_TO_VECTOR stricter to make it clear what types are allowed here. NFC
Make it clear that only integer type with i32 or smaller elements shoudl get to this part of the code.
llvm-svn: 363629
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 42fcb5e92e9..ddcf6896292 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17175,7 +17175,8 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, const X86Subtarget &Subtarget, // Insert the 128-bit vector. return insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); } - assert(OpVT.is128BitVector() && "Expected an SSE type!"); + assert(OpVT.is128BitVector() && OpVT.isInteger() && OpVT != MVT::v2i64 && + "Expected an SSE type!"); // Pass through a v4i32 SCALAR_TO_VECTOR as that's what we use in tblgen. if (OpVT == MVT::v4i32) |
