summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorIgor Breger <igor.breger@intel.com>2017-07-05 11:40:35 +0000
committerIgor Breger <igor.breger@intel.com>2017-07-05 11:40:35 +0000
commit0c979d49eb00dec3b3c63c447d455295443bec8b (patch)
tree1eb72359dbb46b9af87ce822903897e786845b3b
parent3e40b46bf0a31d5cddf0187de96b4d40c0cc2c2f (diff)
downloadbcm5719-llvm-0c979d49eb00dec3b3c63c447d455295443bec8b.tar.gz
bcm5719-llvm-0c979d49eb00dec3b3c63c447d455295443bec8b.zip
[GlobalISel][X86] For now don't handle not trivial function arguments lowering.
llvm-svn: 307142
-rw-r--r--llvm/lib/Target/X86/X86CallLowering.cpp12
1 files changed, 11 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86CallLowering.cpp b/llvm/lib/Target/X86/X86CallLowering.cpp
index bb549dc0488..99aeec67c32 100644
--- a/llvm/lib/Target/X86/X86CallLowering.cpp
+++ b/llvm/lib/Target/X86/X86CallLowering.cpp
@@ -195,8 +195,18 @@ bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
SmallVector<ArgInfo, 8> SplitArgs;
unsigned Idx = 0;
for (auto &Arg : F.args()) {
+
+ // TODO: handle not simple cases.
+ if (Arg.hasAttribute(Attribute::ByVal) ||
+ Arg.hasAttribute(Attribute::InReg) ||
+ Arg.hasAttribute(Attribute::StructRet) ||
+ Arg.hasAttribute(Attribute::SwiftSelf) ||
+ Arg.hasAttribute(Attribute::SwiftError) ||
+ Arg.hasAttribute(Attribute::Nest))
+ return false;
+
ArgInfo OrigArg(VRegs[Idx], Arg.getType());
- setArgFlags(OrigArg, Idx + 1, DL, F);
+ setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
[&](ArrayRef<unsigned> Regs) {
MIRBuilder.buildMerge(VRegs[Idx], Regs);
OpenPOWER on IntegriCloud