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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-06-19 20:22:43 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-06-19 20:22:43 +0000 |
| commit | 0c62bc0324090b2eedb31ad1cf22b0af1c240b83 (patch) | |
| tree | 44c3f29a7cfc198fded513832966cafd9304d188 | |
| parent | 4fc922161684354e928d01e07e222860abf511cc (diff) | |
| download | bcm5719-llvm-0c62bc0324090b2eedb31ad1cf22b0af1c240b83.tar.gz bcm5719-llvm-0c62bc0324090b2eedb31ad1cf22b0af1c240b83.zip | |
Strip trailing whitespace. NFCI.
llvm-svn: 273124
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 88b4535f5e0..4b4d2fab25c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -30281,10 +30281,10 @@ static SDValue detectSADPattern(SDNode *N, SelectionDAG &DAG, // If the reduction vector is at least as wide as the psadbw result, just // bitcast. If it's narrower, truncate - the high i32 of each i64 is zero // anyway. - MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32); + MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32); if (VT.getSizeInBits() >= ResVT.getSizeInBits()) Sad = DAG.getNode(ISD::BITCAST, DL, ResVT, Sad); - else + else Sad = DAG.getNode(ISD::TRUNCATE, DL, VT, Sad); if (VT.getSizeInBits() > ResVT.getSizeInBits()) { |
