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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-02-21 14:51:15 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-02-21 14:51:15 +0000 |
| commit | 0c094f504c2679a5b389fa79a7d10c568f511014 (patch) | |
| tree | 72e93712e4b06937805dab5391b6f59378857347 | |
| parent | 2ee2d2dcb5fee830c277bc8b15ad722402dec210 (diff) | |
| download | bcm5719-llvm-0c094f504c2679a5b389fa79a7d10c568f511014.tar.gz bcm5719-llvm-0c094f504c2679a5b389fa79a7d10c568f511014.zip | |
[X86][SSE] Added SSE41 shuffle combining test file.
Currently just contains one case where we combine to VZEXT_MOVL instead of VZEXT which would avoid the need for a zero vector to be generated
llvm-svn: 295721
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll new file mode 100644 index 00000000000..9352e90952d --- /dev/null +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll @@ -0,0 +1,38 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512F +; +; Combine tests involving SSE41 target shuffles (BLEND,INSERTPS,MOVZX) + +declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) + +; FIXME: We can avoid the zero vector generation if we use PMOVZX instead +define <16 x i8> @combine_vpshufb_as_movzx(<16 x i8> %a0) { +; SSE-LABEL: combine_vpshufb_as_movzx: +; SSE: # BB#0: +; SSE-NEXT: pxor %xmm1, %xmm1 +; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7] +; SSE-NEXT: retq +; +; AVX1-LABEL: combine_vpshufb_as_movzx: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7] +; AVX1-NEXT: retq +; +; AVX2-LABEL: combine_vpshufb_as_movzx: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7] +; AVX2-NEXT: retq +; +; AVX512F-LABEL: combine_vpshufb_as_movzx: +; AVX512F: # BB#0: +; AVX512F-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; AVX512F-NEXT: retq + %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 -1, i8 -1, i8 -1, i8 -1, i8 undef, i8 undef, i8 undef, i8 undef, i8 -1, i8 -1, i8 -1, i8 -1>) + ret <16 x i8> %res0 +} |
