[AArch64][GlobalISel] Add some missing vector support for FP arithmetic ops.

Moved the fneg lowering legalization test from AArch64 to X86, as we want to
specify that it's already legal.

llvm-svn: 352338

5 files changed, 109 insertions, 35 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index 2a42bfff888..8018ba536f2 100644
--- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -119,8 +119,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
   getActionDefinitionsBuilder({G_UADDE, G_USUBE, G_SADDO, G_SSUBO})
       .legalFor({{s32, s1}, {s64, s1}});
 
-  getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMA, G_FMUL, G_FDIV})
-      .legalFor({s32, s64});
+  getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMA, G_FMUL, G_FDIV, G_FNEG})
+    .legalFor({s32, s64, v2s64, v4s32, v2s32});
 
   getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
 
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith.mir
new file mode 100644
index 00000000000..a0be636dfe6
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith.mir
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
+---
+name:            test_fadd_v2s64
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_fadd_v2s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+    ; CHECK: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[COPY]], [[COPY1]]
+    ; CHECK: $q0 = COPY [[FADD]](<2 x s64>)
+    %0:_(<2 x s64>) = COPY $q0
+    %1:_(<2 x s64>) = COPY $q1
+    %2:_(<2 x s64>) = G_FADD %0, %1
+    $q0 = COPY %2(<2 x s64>)
+
+...
+---
+name:            test_fdiv_v2s32
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_fdiv_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+    ; CHECK: [[FDIV:%[0-9]+]]:_(<2 x s32>) = G_FDIV [[COPY]], [[COPY1]]
+    ; CHECK: $d0 = COPY [[FDIV]](<2 x s32>)
+    %0:_(<2 x s32>) = COPY $d0
+    %1:_(<2 x s32>) = COPY $d1
+    %2:_(<2 x s32>) = G_FDIV %0, %1
+    $d0 = COPY %2(<2 x s32>)
+
+...
+---
+name:            test_fsub_v2s32
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_fsub_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+    ; CHECK: [[FSUB:%[0-9]+]]:_(<2 x s32>) = G_FSUB [[COPY]], [[COPY1]]
+    ; CHECK: $d0 = COPY [[FSUB]](<2 x s32>)
+    %0:_(<2 x s32>) = COPY $d0
+    %1:_(<2 x s32>) = COPY $d1
+    %2:_(<2 x s32>) = G_FSUB %0, %1
+    $d0 = COPY %2(<2 x s32>)
+
+...
+---
+name:            test_fneg_v2s32
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_fneg_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+    ; CHECK: [[FNEG:%[0-9]+]]:_(<2 x s32>) = G_FNEG [[COPY]]
+    ; CHECK: $d0 = COPY [[FNEG]](<2 x s32>)
+    %0:_(<2 x s32>) = COPY $d0
+    %1:_(<2 x s32>) = G_FNEG %0
+    $d0 = COPY %1(<2 x s32>)
+
+...
+---
+name:            test_fmul_v4s32
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_fmul_v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
+    ; CHECK: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL [[COPY]], [[COPY1]]
+    ; CHECK: $q0 = COPY [[FMUL]](<4 x s32>)
+    %0:_(<4 x s32>) = COPY $q0
+    %1:_(<4 x s32>) = COPY $q1
+    %2:_(<4 x s32>) = G_FMUL %0, %1
+    $q0 = COPY %2(<4 x s32>)
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
index 271395df27d..48a36566dfa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
@@ -198,6 +198,24 @@ body: |
 ...
 
 ---
+name:            test_uitofp_s64_s8
+body: |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: test_uitofp_s64_s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
+    ; CHECK: $x0 = COPY [[UITOFP]](s64)
+    %0:_(s32) = COPY $w0
+    %1:_(s8) = G_TRUNC %0
+    %2:_(s64) = G_UITOFP %1
+    $x0 = COPY %2
+...
+
+---
 name:            test_sitofp_v4s32
 body: |
   bb.0:
@@ -226,24 +244,6 @@ body: |
 ...
 
 ---
-name:            test_uitofp_s64_s8
-body: |
-  bb.0:
-    liveins: $w0
-    ; CHECK-LABEL: name: test_uitofp_s64_s8
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
-    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
-    ; CHECK: $x0 = COPY [[UITOFP]](s64)
-    %0:_(s32) = COPY $w0
-    %1:_(s8) = G_TRUNC %0
-    %2:_(s64) = G_UITOFP %1
-    $x0 = COPY %2
-...
-
----
 name:            test_sitofp_s32_s16
 body: |
   bb.0:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 717ff430481..d74762aa275 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -271,7 +271,7 @@
 # DEBUG:      .. type index coverage check SKIPPED: no rules defined
 #
 # DEBUG-NEXT: G_FNEG (opcode {{[0-9]+}}): 1 type index
-# DEBUG:      .. type index coverage check SKIPPED: no rules defined
+# DEBUG:      .. the first uncovered type index: 1, OK
 #
 # DEBUG-NEXT: G_FPEXT (opcode {{[0-9]+}}): 2 type indices
 # DEBUG:      .. the first uncovered type index: 2, OK
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fneg.mir
index 59de652d744..dabe3acc93b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fneg.mir
@@ -2,8 +2,7 @@
 # RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
 
 --- |
-  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64--"
+  target triple = "x86_64--"
   define void @test_fneg_f32() {
   entry:
     ret void
@@ -20,15 +19,15 @@ registers:
   - { id: 1, class: _ }
 body:             |
   bb.1:
-    liveins: $s0
+    liveins:
     ; CHECK-LABEL: name: test_fneg_f32
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -0.000000e+00
-    ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[C]], [[COPY]]
-    ; CHECK: $s0 = COPY [[FSUB]](s32)
-    %0(s32) = COPY $s0
+    ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[C]], [[DEF]]
+    ; CHECK: $edi = COPY [[FSUB]](s32)
+    %0(s32) = IMPLICIT_DEF
     %1(s32) = G_FNEG %0
-    $s0 = COPY %1(s32)
+    $edi = COPY %1
 ...
 ---
 name:            test_fneg_f64
@@ -37,13 +36,13 @@ registers:
   - { id: 1, class: _ }
 body:             |
   bb.1:
-    liveins: $d0
+    liveins:
     ; CHECK-LABEL: name: test_fneg_f64
-    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
     ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -0.000000e+00
-    ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[C]], [[COPY]]
-    ; CHECK: $d0 = COPY [[FSUB]](s64)
-    %0(s64) = COPY $d0
+    ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[C]], [[DEF]]
+    ; CHECK: $rdi = COPY [[FSUB]](s64)
+    %0(s64) = G_IMPLICIT_DEF
     %1(s64) = G_FNEG %0
-    $d0 = COPY %1(s64)
+    $rdi = COPY %1
 ...