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authorMatt Arsenault <Matthew.Arsenault@amd.com>2015-02-18 02:15:37 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2015-02-18 02:15:37 +0000
commit0ba644b66b34f453b70f021391702827f5036afe (patch)
tree755d0f7ff05dad4618a684d1e8e958bb318e66c2
parente3dbcf66563e2f48c6d88e96da51589f2bd06316 (diff)
downloadbcm5719-llvm-0ba644b66b34f453b70f021391702827f5036afe.tar.gz
bcm5719-llvm-0ba644b66b34f453b70f021391702827f5036afe.zip
R600/SI: Rename dst encoding field to be consistent with docs
The docs call this vdst instead of just dst. llvm-svn: 229614
-rw-r--r--llvm/lib/Target/R600/SIInstrFormats.td4
-rw-r--r--llvm/lib/Target/R600/VIInstrFormats.td4
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/R600/SIInstrFormats.td b/llvm/lib/Target/R600/SIInstrFormats.td
index 4481156820e..1d561a32349 100644
--- a/llvm/lib/Target/R600/SIInstrFormats.td
+++ b/llvm/lib/Target/R600/SIInstrFormats.td
@@ -300,7 +300,7 @@ class VOP2e <bits<6> op> : Enc32 {
}
class VOP3e <bits<9> op> : Enc64 {
- bits<8> dst;
+ bits<8> vdst;
bits<2> src0_modifiers;
bits<9> src0;
bits<2> src1_modifiers;
@@ -310,7 +310,7 @@ class VOP3e <bits<9> op> : Enc64 {
bits<1> clamp;
bits<2> omod;
- let Inst{7-0} = dst;
+ let Inst{7-0} = vdst;
let Inst{8} = src0_modifiers{1};
let Inst{9} = src1_modifiers{1};
let Inst{10} = src2_modifiers{1};
diff --git a/llvm/lib/Target/R600/VIInstrFormats.td b/llvm/lib/Target/R600/VIInstrFormats.td
index 5ecd2f49ba5..d8738f99263 100644
--- a/llvm/lib/Target/R600/VIInstrFormats.td
+++ b/llvm/lib/Target/R600/VIInstrFormats.td
@@ -105,7 +105,7 @@ class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
}
class VOP3e_vi <bits<10> op> : Enc64 {
- bits<8> dst;
+ bits<8> vdst;
bits<2> src0_modifiers;
bits<9> src0;
bits<2> src1_modifiers;
@@ -115,7 +115,7 @@ class VOP3e_vi <bits<10> op> : Enc64 {
bits<1> clamp;
bits<2> omod;
- let Inst{7-0} = dst;
+ let Inst{7-0} = vdst;
let Inst{8} = src0_modifiers{1};
let Inst{9} = src1_modifiers{1};
let Inst{10} = src2_modifiers{1};
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