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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-24 16:05:55 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-24 16:05:55 +0000 |
| commit | 0b7f2263118cb108467e3afdb8fda332735c1e12 (patch) | |
| tree | 3496d038be61cd8d77435054c8a3a7975960e9e5 | |
| parent | 0e7d8698b5251f42286cd71bd1667cbafe761be1 (diff) | |
| download | bcm5719-llvm-0b7f2263118cb108467e3afdb8fda332735c1e12.tar.gz bcm5719-llvm-0b7f2263118cb108467e3afdb8fda332735c1e12.zip | |
AMDGPU: Fix test after r366913
llvm-svn: 366916
| -rw-r--r-- | llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll | 25 |
1 files changed, 5 insertions, 20 deletions
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll index 9c45cf5aa11..9eb6a909d71 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll @@ -765,14 +765,12 @@ define i32 @extract0_bitcast_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, } ; CHECK-LABEL: @extract0_bitcast_raw_buffer_load_format_v4i32( -; CHECK-NEXT: %tmp = call i32 @llvm.amdgcn.raw.buffer.load.format.i32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0) -; CHECK-NEXT: %tmp2 = bitcast i32 %tmp to float -; CHECK-NEXT: ret float %tmp2 +; CHECK-NEXT: %tmp = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0) +; CHECK-NEXT: ret float %tmp define float @extract0_bitcast_raw_buffer_load_format_v4i32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 { - %tmp = call <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0) - %tmp1 = bitcast <4 x i32> %tmp to <4 x float> - %tmp2 = extractelement <4 x float> %tmp1, i32 0 - ret float %tmp2 + %tmp = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0) + %tmp1 = extractelement <4 x float> %tmp, i32 0 + ret float %tmp1 } ; CHECK-LABEL: @preserve_metadata_extract_elt0_raw_buffer_load_format_v2f32( @@ -790,8 +788,6 @@ declare <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32>, i32, i3 declare <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32) #1 declare <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32) #1 -declare <4 x i32> @llvm.amdgcn.raw.buffer.load.format.v4i32(<4 x i32>, i32, i32, i32) #1 - ; -------------------------------------------------------------------- ; llvm.amdgcn.struct.buffer.load ; -------------------------------------------------------------------- @@ -1242,17 +1238,6 @@ define i32 @extract0_bitcast_struct_buffer_load_format_v4f32(<4 x i32> inreg %rs ret i32 %tmp2 } -; CHECK-LABEL: @extract0_bitcast_struct_buffer_load_format_v4i32( -; CHECK-NEXT: %tmp = call i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0) -; CHECK-NEXT: %tmp2 = bitcast i32 %tmp to float -; CHECK-NEXT: ret float %tmp2 -define float @extract0_bitcast_struct_buffer_load_format_v4i32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 { - %tmp = call <4 x i32> @llvm.amdgcn.struct.buffer.load.format.v4i32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0) - %tmp1 = bitcast <4 x i32> %tmp to <4 x float> - %tmp2 = extractelement <4 x float> %tmp1, i32 0 - ret float %tmp2 -} - ; CHECK-LABEL: @preserve_metadata_extract_elt0_struct_buffer_load_format_v2f32( ; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0), !fpmath !0 ; CHECK-NEXT: ret float %data |
