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| author | Craig Topper <craig.topper@intel.com> | 2017-10-14 04:18:07 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-14 04:18:07 +0000 |
| commit | 0b64e67b0d68ce2b9ce11b8821b8e1d0e83d6d8e (patch) | |
| tree | 07cd7098b9971d1c41f6befed50c9c5c68440f3a | |
| parent | 53b0cb7fa96d4b834b786bd5e9985a0f98d81d07 (diff) | |
| download | bcm5719-llvm-0b64e67b0d68ce2b9ce11b8821b8e1d0e83d6d8e.tar.gz bcm5719-llvm-0b64e67b0d68ce2b9ce11b8821b8e1d0e83d6d8e.zip | |
[X86] Remove TB_NO_REVERSE from VCVTDQ2PDYrr and VCVTPS2PDYrr in the load folding tables.
I believe these were added incorrectly under the belief that the load size was smaller than the input register size, but that's not true.
llvm-svn: 315795
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 00bda1d8ca3..fdac9345d02 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -764,12 +764,12 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, // AVX 256-bit foldable instructions - { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, TB_NO_REVERSE }, + { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 }, { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 }, { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 }, { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 }, { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 }, - { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, TB_NO_REVERSE }, + { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 }, { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 }, { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 }, { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, |
