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| author | Chad Rosier <mcrosier@codeaurora.org> | 2013-11-11 19:11:19 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2013-11-11 19:11:19 +0000 |
| commit | 09f5251c4dd970e503d22619fd5bcfe43ec5eac9 (patch) | |
| tree | ed6775e3ab1153ceb70e2b6e824bebc96711e7f1 | |
| parent | d3684a056652cc61e9e74a24ce94093a443e201b (diff) | |
| download | bcm5719-llvm-09f5251c4dd970e503d22619fd5bcfe43ec5eac9.tar.gz bcm5719-llvm-09f5251c4dd970e503d22619fd5bcfe43ec5eac9.zip | |
[AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.
llvm-svn: 194407
| -rw-r--r-- | clang/include/clang/Basic/arm_neon.td | 4 | ||||
| -rw-r--r-- | clang/test/CodeGen/aarch64-neon-intrinsics.c | 16 |
2 files changed, 10 insertions, 10 deletions
diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index 32bca46726d..cfde22717fd 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -859,9 +859,9 @@ def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">; def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">; // Shift Right And Insert (Immediate) -def SCALAR_SRI_N: SInst<"vsri_n", "ssi", "SlSUl">; +def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">; // Shift Left And Insert (Immediate) -def SCALAR_SLI_N: SInst<"vsli_n", "ssi", "SlSUl">; +def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">; // Signed/Unsigned Saturating Shift Right Narrow (Immediate) def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">; diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics.c b/clang/test/CodeGen/aarch64-neon-intrinsics.c index c59b6ec94fa..3030bd96a26 100644 --- a/clang/test/CodeGen/aarch64-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-neon-intrinsics.c @@ -7616,28 +7616,28 @@ int64_t test_vqshlud_n_s64(int64_t a) { return (int64_t)vqshlud_n_s64(a, 63); } -int64_t test_vsrid_n_s64(int64_t a) { +int64_t test_vsrid_n_s64(int64_t a, int64_t b) { // CHECK-LABEL: test_vsrid_n_s64 // CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63 - return (int64_t)vsrid_n_s64(a, 63); + return (int64_t)vsrid_n_s64(a, b, 63); } -uint64_t test_vsrid_n_u64(uint64_t a) { +uint64_t test_vsrid_n_u64(uint64_t a, uint64_t b) { // CHECK-LABEL: test_vsrid_n_u64 // CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63 - return (uint64_t)vsrid_n_u64(a, 63); + return (uint64_t)vsrid_n_u64(a, b, 63); } -int64_t test_vslid_n_s64(int64_t a) { +int64_t test_vslid_n_s64(int64_t a, int64_t b) { // CHECK-LABEL: test_vslid_n_s64 // CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63 - return (int64_t)vslid_n_s64(a, 63); + return (int64_t)vslid_n_s64(a, b, 63); } -uint64_t test_vslid_n_u64(uint64_t a) { +uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) { // CHECK-LABEL: test_vslid_n_u64 // CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63 - return (uint64_t)vslid_n_u64(a, 63); + return (uint64_t)vslid_n_u64(a, b, 63); } int8_t test_vqshrnh_n_s16(int16_t a) { |
