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author | Chris Lattner <sabre@nondot.org> | 2007-11-19 21:38:03 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2007-11-19 21:38:03 +0000 |
commit | 09c0393d5ebcc4a96566641ec5bc8dadab74e88f (patch) | |
tree | 5f01d1566746ff1a4510e492edb5a868b29f3423 | |
parent | 6fa95ec19d7cea3abe841a268b5c5f89b3df6ba9 (diff) | |
download | bcm5719-llvm-09c0393d5ebcc4a96566641ec5bc8dadab74e88f.tar.gz bcm5719-llvm-09c0393d5ebcc4a96566641ec5bc8dadab74e88f.zip |
ExpandUnalignedLoad doesn't handle vectors right at all apparently.
Fix a couple of problems:
1. Don't assume the VT-1 is a VT that is half the size.
2. Treat vectors of FP in the vector path, not the FP path.
This has a couple of remaining problems before it will work with
the code in PR1811: the code below this change assumes that it can
use extload/shift/or to construct the result, which isn't right for
vectors.
This also doesn't handle vectors of 1 or vectors that aren't pow-2.
llvm-svn: 44243
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index a2f4827870a..32af553b9bf 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -619,13 +619,13 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, SDOperand Ptr = LD->getBasePtr(); MVT::ValueType VT = LD->getValueType(0); MVT::ValueType LoadedVT = LD->getLoadedVT(); - if (MVT::isFloatingPoint(VT)) { + if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) { // Expand to a (misaligned) integer load of the same size, // then bitconvert to floating point. MVT::ValueType intVT; - if (LoadedVT==MVT::f64) + if (LoadedVT == MVT::f64) intVT = MVT::i64; - else if (LoadedVT==MVT::f32) + else if (LoadedVT == MVT::f32) intVT = MVT::i32; else assert(0 && "Unaligned load of unsupported floating point type"); @@ -641,11 +641,25 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); } - assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type."); - MVT::ValueType NewLoadedVT = LoadedVT - 1; - int NumBits = MVT::getSizeInBits(NewLoadedVT); - int Alignment = LD->getAlignment(); - int IncrementSize = NumBits / 8; + assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) && + "Unaligned load of unsupported type."); + + // Compute the new VT that is half the size of the old one. We either have an + // integer MVT or we have a vector MVT. + unsigned NumBits = MVT::getSizeInBits(LoadedVT); + MVT::ValueType NewLoadedVT; + if (!MVT::isVector(LoadedVT)) { + NewLoadedVT = MVT::getIntegerType(NumBits/2); + } else { + // FIXME: This is not right for <1 x anything> it is also not right for + // non-power-of-two vectors. + NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT), + MVT::getVectorNumElements(LoadedVT)/2); + } + NumBits >>= 1; + + unsigned Alignment = LD->getAlignment(); + unsigned IncrementSize = NumBits / 8; ISD::LoadExtType HiExtType = LD->getExtensionType(); // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. |