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authorMikhail Dvoretckii <mikhail.dvoretckii@intel.com>2018-06-22 08:28:05 +0000
committerMikhail Dvoretckii <mikhail.dvoretckii@intel.com>2018-06-22 08:28:05 +0000
commit09635620836c4fb88cee21df15af77d6427fc3ac (patch)
tree5326d31498c3be8e49efd0fb9688d0a469021e1b
parentac5fa6605c8ee539bf61075b5851d87bca413c4c (diff)
downloadbcm5719-llvm-09635620836c4fb88cee21df15af77d6427fc3ac.tar.gz
bcm5719-llvm-09635620836c4fb88cee21df15af77d6427fc3ac.zip
[X86] Changing the check for valid inputs in combineScalarToVector
Changing the logic of scalar mask folding to check for valid input types rather than against invalid ones, making it more robust and fixing PR37879. Differential Revision: https://reviews.llvm.org/D48366 llvm-svn: 335323
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp11
-rw-r--r--llvm/test/CodeGen/X86/pr37879.ll10
2 files changed, 15 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 314a944858b..27a0c51e3fd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -39229,7 +39229,8 @@ static SDValue combineScalarToVector(SDNode *N, SelectionDAG &DAG) {
if (C->getAPIntValue().isOneValue()) {
SDValue Mask = Src.getOperand(0);
if (Mask.getOpcode() == ISD::TRUNCATE &&
- Mask.getOperand(0).getValueType() != MVT::i16)
+ (Mask.getOperand(0).getValueType() == MVT::i8 ||
+ Mask.getOperand(0).getValueType() == MVT::i32))
Mask = Mask.getOperand(0);
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), MVT::v1i1, Mask);
}
@@ -39243,11 +39244,11 @@ static SDValue combineScalarToVector(SDNode *N, SelectionDAG &DAG) {
if (C->getAPIntValue().isOneValue()) {
SDValue Mask = Src.getOperand(0).getOperand(0);
if (Mask.getOpcode() == ISD::TRUNCATE &&
- Mask.getOperand(0).getValueType() != MVT::i16)
+ (Mask.getOperand(0).getValueType() == MVT::i8 ||
+ Mask.getOperand(0).getValueType() == MVT::i32))
Mask = Mask.getOperand(0);
- // Check if the initial value is an i16. scalar_to_vector fails to
- // select for that type, so the combine should be aborted.
- if (Mask.getValueType() == MVT::i16)
+ // Check if the initial value is of a legal type for scalar_to_vector.
+ if (Mask.getValueType() != MVT::i8 && Mask.getValueType() != MVT::i32)
return SDValue();
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), MVT::v1i1, Mask);
}
diff --git a/llvm/test/CodeGen/X86/pr37879.ll b/llvm/test/CodeGen/X86/pr37879.ll
index 9beb6dbae00..033cad8ea0c 100644
--- a/llvm/test/CodeGen/X86/pr37879.ll
+++ b/llvm/test/CodeGen/X86/pr37879.ll
@@ -1,7 +1,15 @@
-; XFAIL: *
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 < %s -mtriple=x86_64-apple-darwin -mattr=+avx512bw | FileCheck %s
define double @foo(i32** nocapture readonly) #0 {
+; CHECK-LABEL: foo:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movq (%rax), %rax
+; CHECK-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1
+; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: kmovd %eax, %k1
+; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
+; CHECK-NEXT: retq
%2 = load i64, i64* undef, align 8
%3 = and i64 %2, 1
%4 = icmp eq i64 %3, 0
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