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authorCraig Topper <craig.topper@intel.com>2018-11-30 06:23:55 +0000
committerCraig Topper <craig.topper@intel.com>2018-11-30 06:23:55 +0000
commit0850e8a6b647323ba184d4c63a8d500b3a7ec013 (patch)
tree906fe82efcd00f083fec94f69d56cf6e168b94aa
parent6e4dc6f23f0e755b29b1e9bba76632a536f5f534 (diff)
downloadbcm5719-llvm-0850e8a6b647323ba184d4c63a8d500b3a7ec013.tar.gz
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[X86] Fix a couple types in SimplifyDemandedVectorEltsForTargetNode. NFCI
We had a EVT variable capturing the result of getSimpleValueType which returns an MVT. Another place using EVT that could have been MVT. And an 'int' that should be 'unsigned'. llvm-svn: 347959
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 54d52277625..bfd8f9e3c56 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -32253,10 +32253,10 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
case X86ISD::VSRA: {
// We only need the bottom 64-bits of the (128-bit) shift amount.
SDValue Amt = Op.getOperand(1);
- EVT AmtVT = Amt.getSimpleValueType();
+ MVT AmtVT = Amt.getSimpleValueType();
assert(AmtVT.is128BitVector() && "Unexpected value type");
APInt AmtUndef, AmtZero;
- int NumAmtElts = AmtVT.getVectorNumElements();
+ unsigned NumAmtElts = AmtVT.getVectorNumElements();
APInt AmtElts = APInt::getLowBitsSet(NumAmtElts, NumAmtElts / 2);
if (SimplifyDemandedVectorElts(Amt, AmtElts, AmtUndef, AmtZero, TLO,
Depth + 1))
@@ -32266,7 +32266,7 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
case X86ISD::CVTSI2P:
case X86ISD::CVTUI2P: {
SDValue Src = Op.getOperand(0);
- EVT SrcVT = Src.getValueType();
+ MVT SrcVT = Src.getSimpleValueType();
APInt SrcUndef, SrcZero;
APInt SrcElts = DemandedElts.zextOrTrunc(SrcVT.getVectorNumElements());
if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO,
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