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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-01-30 18:10:21 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-01-30 18:10:21 +0000 |
| commit | 073f089c6e5ba77bc398cc2d1b106cebbbd2429f (patch) | |
| tree | 8c8314af83dc17d0746cf202831b35f43c314191 | |
| parent | a9f488588dea9b64727b4bbea078ad63fa5829a8 (diff) | |
| download | bcm5719-llvm-073f089c6e5ba77bc398cc2d1b106cebbbd2429f.tar.gz bcm5719-llvm-073f089c6e5ba77bc398cc2d1b106cebbbd2429f.zip | |
[X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP
Similar to D42437, XOP supports variable shift for v16i8/v8i16/v4i32/v2i64 types.
Differential Revision: https://reviews.llvm.org/D42526
llvm-svn: 323797
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll | 9 |
2 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 925796cae7a..4c80b86d449 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -25593,6 +25593,11 @@ bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const { if (Bits == 8) return false; + // XOP has v16i8/v8i16/v4i32/v2i64 variable vector shifts. + if (Subtarget.hasXOP() && Ty->getPrimitiveSizeInBits() == 128 && + (Bits == 8 || Bits == 16 || Bits == 32 || Bits == 64)) + return false; + // AVX2 has vpsllv[dq] instructions (and other shifts) that make variable // shifts just as cheap as scalar ones. if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64)) diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll index 74e73e87619..112b63dd773 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll @@ -45,8 +45,7 @@ define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) { ; CHECK-XOP: if_true: ; CHECK-XOP-NEXT: ret <8 x i16> [[MASK]] ; CHECK-XOP: if_false: -; CHECK-XOP-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer -; CHECK-XOP-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]] +; CHECK-XOP-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]] ; CHECK-XOP-NEXT: ret <8 x i16> [[RES]] ; ; CHECK-AVX2-LABEL: @test_16bit( @@ -117,8 +116,7 @@ define <4 x i32> @test_32bit(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) { ; CHECK-XOP: if_true: ; CHECK-XOP-NEXT: ret <4 x i32> [[MASK]] ; CHECK-XOP: if_false: -; CHECK-XOP-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0> -; CHECK-XOP-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[TMP1]] +; CHECK-XOP-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]] ; CHECK-XOP-NEXT: ret <4 x i32> [[RES]] ; ; CHECK-AVX-LABEL: @test_32bit( @@ -158,8 +156,7 @@ define <2 x i64> @test_64bit(<2 x i64> %lhs, <2 x i64> %tmp, i1 %tst) { ; CHECK-XOP: if_true: ; CHECK-XOP-NEXT: ret <2 x i64> [[MASK]] ; CHECK-XOP: if_false: -; CHECK-XOP-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <2 x i32> zeroinitializer -; CHECK-XOP-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[TMP1]] +; CHECK-XOP-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]] ; CHECK-XOP-NEXT: ret <2 x i64> [[RES]] ; ; CHECK-AVX-LABEL: @test_64bit( |
