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authorChuang-Yu Cheng <cycheng@multicorewareinc.com>2016-04-26 07:38:24 +0000
committerChuang-Yu Cheng <cycheng@multicorewareinc.com>2016-04-26 07:38:24 +0000
commit0600e8d759b4addedc5a0fbdf6a7e52d4504ec4f (patch)
treeb543f784f54809dad9aa45e14f89755ccd34a1de
parent9163f4997aa2069af9eee1b0f2689df143d014ee (diff)
downloadbcm5719-llvm-0600e8d759b4addedc5a0fbdf6a7e52d4504ec4f.tar.gz
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[ppc64] Reenable sibling call optimization on ppc64 since fixed tsan library tail-call issue
print-stack-trace.cc test failure of compiler-rt has been fixed by r266869 (http://reviews.llvm.org/D19148), so reenable sibling call optimization on ppc64 Reviewers: nemanjai kbarton llvm-svn: 267527
-rw-r--r--llvm/docs/ReleaseNotes.rst1
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp2
2 files changed, 2 insertions, 1 deletions
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index df34d2a20da..6d1f74c7d0a 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -114,6 +114,7 @@ Changes to the PowerPC Target
Moved some optimizations from O3 to O2 (D18562)
+* Enable sibling call optimization on ppc64 ELFv1/ELFv2 abi
Changes to the X86 Target
-------------------------
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 0ae4e5ebd09..72335a4f999 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -55,7 +55,7 @@ cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hi
static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
-static cl::opt<bool> DisableSCO("disable-ppc-sco", cl::init(true),
+static cl::opt<bool> DisableSCO("disable-ppc-sco",
cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
STATISTIC(NumTailCalls, "Number of tail calls");
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