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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2016-11-08 20:18:41 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2016-11-08 20:18:41 +0000
commit05effca2d8b78216e054e37cecd46bedb92c97fd (patch)
tree9c96a70b341dd40361b7238ef83ecb4fd09206fd
parent4006e09d1d0e910e1379718ba38a9a052b86b852 (diff)
downloadbcm5719-llvm-05effca2d8b78216e054e37cecd46bedb92c97fd.tar.gz
bcm5719-llvm-05effca2d8b78216e054e37cecd46bedb92c97fd.zip
[SystemZ] Add missing FP extension instructions
This completes assembler / disassembler support for all BFP instructions provided by the floating-point extensions facility. The instructions added here are not currently used for codegen. llvm-svn: 286285
-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrFP.td24
-rw-r--r--llvm/lib/Target/SystemZ/SystemZScheduleZ13.td12
-rw-r--r--llvm/lib/Target/SystemZ/SystemZScheduleZ196.td12
-rw-r--r--llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td12
-rw-r--r--llvm/test/MC/Disassembler/SystemZ/insns.txt216
-rw-r--r--llvm/test/MC/SystemZ/insn-bad-z196.s180
-rw-r--r--llvm/test/MC/SystemZ/insn-bad.s58
-rw-r--r--llvm/test/MC/SystemZ/insn-good-z196.s168
8 files changed, 664 insertions, 18 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFP.td b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
index f731f70e47c..6ef7c9c9564 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
@@ -189,6 +189,18 @@ def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>;
def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>;
def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>;
+// The FP extension feature provides versions of the above that allow
+// specifying rounding mode and inexact-exception suppression flags.
+let Predicates = [FeatureFPExtension] in {
+ def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32, GR32>;
+ def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64, GR32>;
+ def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>;
+
+ def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32, GR64>;
+ def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64, GR64>;
+ def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>;
+}
+
// Convert am unsigned integer register value to a floating-point one.
let Predicates = [FeatureFPExtension] in {
def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>;
@@ -229,6 +241,18 @@ def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;
def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;
def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
+// The FP extension feature provides versions of the above that allow
+// also specifying the inexact-exception suppression flag.
+let Predicates = [FeatureFPExtension], Defs = [CC] in {
+ def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>;
+ def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>;
+ def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>;
+
+ def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>;
+ def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>;
+ def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>;
+}
+
// Convert a floating-point register value to an unsigned integer value.
let Predicates = [FeatureFPExtension] in {
let Defs = [CC] in {
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index 11ceca17ded..d5b2c127995 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -698,17 +698,17 @@ def : InstRW<[VecBF2, VecBF2, LSU, Lat12 , GroupAlone], (instregex "LX(D|E)B$")>
def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "LX(D|E)BR$")>;
// Convert from fixed / logical
-def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CE(F|G)BR$")>;
-def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CD(F|G)BR$")>;
-def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CX(F|G)BR$")>;
+def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CE(F|G)BR(A)?$")>;
+def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CD(F|G)BR(A)?$")>;
+def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CX(F|G)BR(A)?$")>;
def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CEL(F|G)BR$")>;
def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CDL(F|G)BR$")>;
def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CXL(F|G)BR$")>;
// Convert to fixed / logical
-def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CF(E|D)BR$")>;
-def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CG(E|D)BR$")>;
-def : InstRW<[FXb, VecDF, VecDF, Lat20, BeginGroup], (instregex "C(F|G)XBR$")>;
+def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CF(E|D)BR(A)?$")>;
+def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CG(E|D)BR(A)?$")>;
+def : InstRW<[FXb, VecDF, VecDF, Lat20, BeginGroup], (instregex "C(F|G)XBR(A)?$")>;
def : InstRW<[FXb, VecBF, Lat11, GroupAlone], (instregex "CLFEBR$")>;
def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CLFDBR$")>;
def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CLG(E|D)BR$")>;
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index d7022fbc81c..c4c377e0702 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -648,17 +648,17 @@ def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
// Convert from fixed / logical
-def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR$")>;
-def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR$")>;
-def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR$")>;
+def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A)?$")>;
+def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A)?$")>;
+def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A)?$")>;
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
// Convert to fixed / logical
-def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR$")>;
-def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR$")>;
-def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR$")>;
+def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A)?$")>;
+def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A)?$")>;
+def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A)?$")>;
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index fb1c17e4846..08a49b9e479 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -676,17 +676,17 @@ def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
// Convert from fixed / logical
-def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR$")>;
-def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR$")>;
-def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR$")>;
+def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A?)$")>;
+def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A?)$")>;
+def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A?)$")>;
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
// Convert to fixed / logical
-def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR$")>;
-def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR$")>;
-def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR$")>;
+def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A?)$")>;
+def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A?)$")>;
+def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A?)$")>;
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index c8b49df8d39..cb163271b6c 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -1042,6 +1042,24 @@
# CHECK: cdfbr %f15, %r15
0xb3 0x95 0x00 0xff
+# CHECK: cdfbra %f0, 0, %r0, 1
+0xb3 0x95 0x01 0x00
+
+# CHECK: cdfbra %f0, 0, %r0, 15
+0xb3 0x95 0x0f 0x00
+
+# CHECK: cdfbra %f0, 0, %r15, 1
+0xb3 0x95 0x01 0x0f
+
+# CHECK: cdfbra %f0, 15, %r0, 1
+0xb3 0x95 0xf1 0x00
+
+# CHECK: cdfbra %f4, 5, %r6, 7
+0xb3 0x95 0x57 0x46
+
+# CHECK: cdfbra %f15, 0, %r0, 1
+0xb3 0x95 0x01 0xf0
+
# CHECK: cdgbr %f0, %r0
0xb3 0xa5 0x00 0x00
@@ -1057,6 +1075,24 @@
# CHECK: cdgbr %f15, %r15
0xb3 0xa5 0x00 0xff
+# CHECK: cdgbra %f0, 0, %r0, 1
+0xb3 0xa5 0x01 0x00
+
+# CHECK: cdgbra %f0, 0, %r0, 15
+0xb3 0xa5 0x0f 0x00
+
+# CHECK: cdgbra %f0, 0, %r15, 1
+0xb3 0xa5 0x01 0x0f
+
+# CHECK: cdgbra %f0, 15, %r0, 1
+0xb3 0xa5 0xf1 0x00
+
+# CHECK: cdgbra %f4, 5, %r6, 7
+0xb3 0xa5 0x57 0x46
+
+# CHECK: cdgbra %f15, 0, %r0, 1
+0xb3 0xa5 0x01 0xf0
+
# CHECK: cdlfbr %f0, 0, %r0, 1
0xb3 0x91 0x01 0x00
@@ -1141,6 +1177,24 @@
# CHECK: cefbr %f15, %r15
0xb3 0x94 0x00 0xff
+# CHECK: cefbra %f0, 0, %r0, 1
+0xb3 0x94 0x01 0x00
+
+# CHECK: cefbra %f0, 0, %r0, 15
+0xb3 0x94 0x0f 0x00
+
+# CHECK: cefbra %f0, 0, %r15, 1
+0xb3 0x94 0x01 0x0f
+
+# CHECK: cefbra %f0, 15, %r0, 1
+0xb3 0x94 0xf1 0x00
+
+# CHECK: cefbra %f4, 5, %r6, 7
+0xb3 0x94 0x57 0x46
+
+# CHECK: cefbra %f15, 0, %r0, 1
+0xb3 0x94 0x01 0xf0
+
# CHECK: cegbr %f0, %r0
0xb3 0xa4 0x00 0x00
@@ -1156,6 +1210,24 @@
# CHECK: cegbr %f15, %r15
0xb3 0xa4 0x00 0xff
+# CHECK: cegbra %f0, 0, %r0, 1
+0xb3 0xa4 0x01 0x00
+
+# CHECK: cegbra %f0, 0, %r0, 15
+0xb3 0xa4 0x0f 0x00
+
+# CHECK: cegbra %f0, 0, %r15, 1
+0xb3 0xa4 0x01 0x0f
+
+# CHECK: cegbra %f0, 15, %r0, 1
+0xb3 0xa4 0xf1 0x00
+
+# CHECK: cegbra %f4, 5, %r6, 7
+0xb3 0xa4 0x57 0x46
+
+# CHECK: cegbra %f15, 0, %r0, 1
+0xb3 0xa4 0x01 0xf0
+
# CHECK: celfbr %f0, 0, %r0, 1
0xb3 0x90 0x01 0x00
@@ -1207,6 +1279,24 @@
# CHECK: cfdbr %r15, 0, %f0
0xb3 0x99 0x00 0xf0
+# CHECK: cfdbra %r0, 0, %f0, 1
+0xb3 0x99 0x01 0x00
+
+# CHECK: cfdbra %r0, 0, %f0, 15
+0xb3 0x99 0x0f 0x00
+
+# CHECK: cfdbra %r0, 0, %f15, 1
+0xb3 0x99 0x01 0x0f
+
+# CHECK: cfdbra %r0, 15, %f0, 1
+0xb3 0x99 0xf1 0x00
+
+# CHECK: cfdbra %r4, 5, %f6, 7
+0xb3 0x99 0x57 0x46
+
+# CHECK: cfdbra %r15, 0, %f0, 1
+0xb3 0x99 0x01 0xf0
+
# CHECK: cfebr %r0, 0, %f0
0xb3 0x98 0x00 0x00
@@ -1222,6 +1312,24 @@
# CHECK: cfebr %r15, 0, %f0
0xb3 0x98 0x00 0xf0
+# CHECK: cfebra %r0, 0, %f0, 1
+0xb3 0x98 0x01 0x00
+
+# CHECK: cfebra %r0, 0, %f0, 15
+0xb3 0x98 0x0f 0x00
+
+# CHECK: cfebra %r0, 0, %f15, 1
+0xb3 0x98 0x01 0x0f
+
+# CHECK: cfebra %r0, 15, %f0, 1
+0xb3 0x98 0xf1 0x00
+
+# CHECK: cfebra %r4, 5, %f6, 7
+0xb3 0x98 0x57 0x46
+
+# CHECK: cfebra %r15, 0, %f0, 1
+0xb3 0x98 0x01 0xf0
+
# CHECK: cfi %r0, -2147483648
0xc2 0x0d 0x80 0x00 0x00 0x00
@@ -1255,6 +1363,24 @@
# CHECK: cfxbr %r15, 0, %f0
0xb3 0x9a 0x00 0xf0
+# CHECK: cfxbra %r0, 0, %f0, 1
+0xb3 0x9a 0x01 0x00
+
+# CHECK: cfxbra %r0, 0, %f0, 15
+0xb3 0x9a 0x0f 0x00
+
+# CHECK: cfxbra %r0, 0, %f13, 1
+0xb3 0x9a 0x01 0x0d
+
+# CHECK: cfxbra %r0, 15, %f0, 1
+0xb3 0x9a 0xf1 0x00
+
+# CHECK: cfxbra %r4, 5, %f8, 9
+0xb3 0x9a 0x59 0x48
+
+# CHECK: cfxbra %r15, 0, %f0, 1
+0xb3 0x9a 0x01 0xf0
+
# CHECK: cgdbr %r0, 0, %f0
0xb3 0xa9 0x00 0x00
@@ -1270,6 +1396,24 @@
# CHECK: cgdbr %r15, 0, %f0
0xb3 0xa9 0x00 0xf0
+# CHECK: cgdbra %r0, 0, %f0, 1
+0xb3 0xa9 0x01 0x00
+
+# CHECK: cgdbra %r0, 0, %f0, 15
+0xb3 0xa9 0x0f 0x00
+
+# CHECK: cgdbra %r0, 0, %f15, 1
+0xb3 0xa9 0x01 0x0f
+
+# CHECK: cgdbra %r0, 15, %f0, 1
+0xb3 0xa9 0xf1 0x00
+
+# CHECK: cgdbra %r4, 5, %f6, 7
+0xb3 0xa9 0x57 0x46
+
+# CHECK: cgdbra %r15, 0, %f0, 1
+0xb3 0xa9 0x01 0xf0
+
# CHECK: cgebr %r0, 0, %f0
0xb3 0xa8 0x00 0x00
@@ -1285,6 +1429,24 @@
# CHECK: cgebr %r15, 0, %f0
0xb3 0xa8 0x00 0xf0
+# CHECK: cgebra %r0, 0, %f0, 1
+0xb3 0xa8 0x01 0x00
+
+# CHECK: cgebra %r0, 0, %f0, 15
+0xb3 0xa8 0x0f 0x00
+
+# CHECK: cgebra %r0, 0, %f15, 1
+0xb3 0xa8 0x01 0x0f
+
+# CHECK: cgebra %r0, 15, %f0, 1
+0xb3 0xa8 0xf1 0x00
+
+# CHECK: cgebra %r4, 5, %f6, 7
+0xb3 0xa8 0x57 0x46
+
+# CHECK: cgebra %r15, 0, %f0, 1
+0xb3 0xa8 0x01 0xf0
+
# CHECK: cgfi %r0, -2147483648
0xc2 0x0c 0x80 0x00 0x00 0x00
@@ -1657,6 +1819,24 @@
# CHECK: cgxbr %r15, 0, %f0
0xb3 0xaa 0x00 0xf0
+# CHECK: cgxbra %r0, 0, %f0, 1
+0xb3 0xaa 0x01 0x00
+
+# CHECK: cgxbra %r0, 0, %f0, 15
+0xb3 0xaa 0x0f 0x00
+
+# CHECK: cgxbra %r0, 0, %f13, 1
+0xb3 0xaa 0x01 0x0d
+
+# CHECK: cgxbra %r0, 15, %f0, 1
+0xb3 0xaa 0xf1 0x00
+
+# CHECK: cgxbra %r4, 5, %f8, 9
+0xb3 0xaa 0x59 0x48
+
+# CHECK: cgxbra %r15, 0, %f0, 1
+0xb3 0xaa 0x01 0xf0
+
# CHECK: chf %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0xcd
@@ -3022,6 +3202,24 @@
# CHECK: cxfbr %f13, %r15
0xb3 0x96 0x00 0xdf
+# CHECK: cxfbra %f0, 0, %r0, 1
+0xb3 0x96 0x01 0x00
+
+# CHECK: cxfbra %f0, 0, %r0, 15
+0xb3 0x96 0x0f 0x00
+
+# CHECK: cxfbra %f0, 0, %r15, 1
+0xb3 0x96 0x01 0x0f
+
+# CHECK: cxfbra %f0, 15, %r0, 1
+0xb3 0x96 0xf1 0x00
+
+# CHECK: cxfbra %f4, 5, %r6, 7
+0xb3 0x96 0x57 0x46
+
+# CHECK: cxfbra %f13, 0, %r0, 1
+0xb3 0x96 0x01 0xd0
+
# CHECK: cxgbr %f0, %r0
0xb3 0xa6 0x00 0x00
@@ -3037,6 +3235,24 @@
# CHECK: cxgbr %f13, %r15
0xb3 0xa6 0x00 0xdf
+# CHECK: cxgbra %f0, 0, %r0, 1
+0xb3 0xa6 0x01 0x00
+
+# CHECK: cxgbra %f0, 0, %r0, 15
+0xb3 0xa6 0x0f 0x00
+
+# CHECK: cxgbra %f0, 0, %r15, 1
+0xb3 0xa6 0x01 0x0f
+
+# CHECK: cxgbra %f0, 15, %r0, 1
+0xb3 0xa6 0xf1 0x00
+
+# CHECK: cxgbra %f4, 5, %r6, 7
+0xb3 0xa6 0x57 0x46
+
+# CHECK: cxgbra %f13, 0, %r0, 1
+0xb3 0xa6 0x01 0xd0
+
# CHECK: cxlfbr %f0, 0, %r0, 1
0xb3 0x92 0x01 0x00
diff --git a/llvm/test/MC/SystemZ/insn-bad-z196.s b/llvm/test/MC/SystemZ/insn-bad-z196.s
index b329d84da28..b2c37e172a8 100644
--- a/llvm/test/MC/SystemZ/insn-bad-z196.s
+++ b/llvm/test/MC/SystemZ/insn-bad-z196.s
@@ -35,6 +35,34 @@
aih %r0, (1 << 31)
#CHECK: error: invalid operand
+#CHECK: cdfbra %f0, 0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: cdfbra %f0, 0, %r0, 16
+#CHECK: error: invalid operand
+#CHECK: cdfbra %f0, -1, %r0, 0
+#CHECK: error: invalid operand
+#CHECK: cdfbra %f0, 16, %r0, 0
+
+ cdfbra %f0, 0, %r0, -1
+ cdfbra %f0, 0, %r0, 16
+ cdfbra %f0, -1, %r0, 0
+ cdfbra %f0, 16, %r0, 0
+
+#CHECK: error: invalid operand
+#CHECK: cdgbra %f0, 0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: cdgbra %f0, 0, %r0, 16
+#CHECK: error: invalid operand
+#CHECK: cdgbra %f0, -1, %r0, 0
+#CHECK: error: invalid operand
+#CHECK: cdgbra %f0, 16, %r0, 0
+
+ cdgbra %f0, 0, %r0, -1
+ cdgbra %f0, 0, %r0, 16
+ cdgbra %f0, -1, %r0, 0
+ cdgbra %f0, 16, %r0, 0
+
+#CHECK: error: invalid operand
#CHECK: cdlfbr %f0, 0, %r0, -1
#CHECK: error: invalid operand
#CHECK: cdlfbr %f0, 0, %r0, 16
@@ -63,6 +91,34 @@
cdlgbr %f0, 16, %r0, 0
#CHECK: error: invalid operand
+#CHECK: cefbra %f0, 0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: cefbra %f0, 0, %r0, 16
+#CHECK: error: invalid operand
+#CHECK: cefbra %f0, -1, %r0, 0
+#CHECK: error: invalid operand
+#CHECK: cefbra %f0, 16, %r0, 0
+
+ cefbra %f0, 0, %r0, -1
+ cefbra %f0, 0, %r0, 16
+ cefbra %f0, -1, %r0, 0
+ cefbra %f0, 16, %r0, 0
+
+#CHECK: error: invalid operand
+#CHECK: cegbra %f0, 0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: cegbra %f0, 0, %r0, 16
+#CHECK: error: invalid operand
+#CHECK: cegbra %f0, -1, %r0, 0
+#CHECK: error: invalid operand
+#CHECK: cegbra %f0, 16, %r0, 0
+
+ cegbra %f0, 0, %r0, -1
+ cegbra %f0, 0, %r0, 16
+ cegbra %f0, -1, %r0, 0
+ cegbra %f0, 16, %r0, 0
+
+#CHECK: error: invalid operand
#CHECK: celfbr %f0, 0, %r0, -1
#CHECK: error: invalid operand
#CHECK: celfbr %f0, 0, %r0, 16
@@ -91,6 +147,96 @@
celgbr %f0, 16, %r0, 0
#CHECK: error: invalid operand
+#CHECK: cfdbra %r0, 0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: cfdbra %r0, 0, %f0, 16
+#CHECK: error: invalid operand
+#CHECK: cfdbra %r0, -1, %f0, 0
+#CHECK: error: invalid operand
+#CHECK: cfdbra %r0, 16, %f0, 0
+
+ cfdbra %r0, 0, %f0, -1
+ cfdbra %r0, 0, %f0, 16
+ cfdbra %r0, -1, %f0, 0
+ cfdbra %r0, 16, %f0, 0
+
+#CHECK: error: invalid operand
+#CHECK: cfebra %r0, 0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: cfebra %r0, 0, %f0, 16
+#CHECK: error: invalid operand
+#CHECK: cfebra %r0, -1, %f0, 0
+#CHECK: error: invalid operand
+#CHECK: cfebra %r0, 16, %f0, 0
+
+ cfebra %r0, 0, %f0, -1
+ cfebra %r0, 0, %f0, 16
+ cfebra %r0, -1, %f0, 0
+ cfebra %r0, 16, %f0, 0
+
+#CHECK: error: invalid operand
+#CHECK: cfxbra %r0, 0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: cfxbra %r0, 0, %f0, 16
+#CHECK: error: invalid operand
+#CHECK: cfxbra %r0, -1, %f0, 0
+#CHECK: error: invalid operand
+#CHECK: cfxbra %r0, 16, %f0, 0
+#CHECK: error: invalid register pair
+#CHECK: cfxbra %r0, 0, %f14, 0
+
+ cfxbra %r0, 0, %f0, -1
+ cfxbra %r0, 0, %f0, 16
+ cfxbra %r0, -1, %f0, 0
+ cfxbra %r0, 16, %f0, 0
+ cfxbra %r0, 0, %f14, 0
+
+#CHECK: error: invalid operand
+#CHECK: cgdbra %r0, 0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: cgdbra %r0, 0, %f0, 16
+#CHECK: error: invalid operand
+#CHECK: cgdbra %r0, -1, %f0, 0
+#CHECK: error: invalid operand
+#CHECK: cgdbra %r0, 16, %f0, 0
+
+ cgdbra %r0, 0, %f0, -1
+ cgdbra %r0, 0, %f0, 16
+ cgdbra %r0, -1, %f0, 0
+ cgdbra %r0, 16, %f0, 0
+
+#CHECK: error: invalid operand
+#CHECK: cgebra %r0, 0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: cgebra %r0, 0, %f0, 16
+#CHECK: error: invalid operand
+#CHECK: cgebra %r0, -1, %f0, 0
+#CHECK: error: invalid operand
+#CHECK: cgebra %r0, 16, %f0, 0
+
+ cgebra %r0, 0, %f0, -1
+ cgebra %r0, 0, %f0, 16
+ cgebra %r0, -1, %f0, 0
+ cgebra %r0, 16, %f0, 0
+
+#CHECK: error: invalid operand
+#CHECK: cgxbra %r0, 0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: cgxbra %r0, 0, %f0, 16
+#CHECK: error: invalid operand
+#CHECK: cgxbra %r0, -1, %f0, 0
+#CHECK: error: invalid operand
+#CHECK: cgxbra %r0, 16, %f0, 0
+#CHECK: error: invalid register pair
+#CHECK: cgxbra %r0, 0, %f14, 0
+
+ cgxbra %r0, 0, %f0, -1
+ cgxbra %r0, 0, %f0, 16
+ cgxbra %r0, -1, %f0, 0
+ cgxbra %r0, 16, %f0, 0
+ cgxbra %r0, 0, %f14, 0
+
+#CHECK: error: invalid operand
#CHECK: chf %r0, -524289
#CHECK: error: invalid operand
#CHECK: chf %r0, 524288
@@ -213,6 +359,40 @@
clih %r0, (1 << 32)
#CHECK: error: invalid operand
+#CHECK: cxfbra %f0, 0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: cxfbra %f0, 0, %r0, 16
+#CHECK: error: invalid operand
+#CHECK: cxfbra %f0, -1, %r0, 0
+#CHECK: error: invalid operand
+#CHECK: cxfbra %f0, 16, %r0, 0
+#CHECK: error: invalid register pair
+#CHECK: cxfbra %f2, 0, %r0, 0
+
+ cxfbra %f0, 0, %r0, -1
+ cxfbra %f0, 0, %r0, 16
+ cxfbra %f0, -1, %r0, 0
+ cxfbra %f0, 16, %r0, 0
+ cxfbra %f2, 0, %r0, 0
+
+#CHECK: error: invalid operand
+#CHECK: cxgbra %f0, 0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: cxgbra %f0, 0, %r0, 16
+#CHECK: error: invalid operand
+#CHECK: cxgbra %f0, -1, %r0, 0
+#CHECK: error: invalid operand
+#CHECK: cxgbra %f0, 16, %r0, 0
+#CHECK: error: invalid register pair
+#CHECK: cxgbra %f2, 0, %r0, 0
+
+ cxgbra %f0, 0, %r0, -1
+ cxgbra %f0, 0, %r0, 16
+ cxgbra %f0, -1, %r0, 0
+ cxgbra %f0, 16, %r0, 0
+ cxgbra %f2, 0, %r0, 0
+
+#CHECK: error: invalid operand
#CHECK: cxlfbr %f0, 0, %r0, -1
#CHECK: error: invalid operand
#CHECK: cxlfbr %f0, 0, %r0, 16
diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s
index c5b1991a9d9..49b4a0b8233 100644
--- a/llvm/test/MC/SystemZ/insn-bad.s
+++ b/llvm/test/MC/SystemZ/insn-bad.s
@@ -447,6 +447,16 @@
cdb %f0, 4096
#CHECK: error: instruction requires: fp-extension
+#CHECK: cdfbra %f0, 0, %r0, 0
+
+ cdfbra %f0, 0, %r0, 0
+
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cdgbra %f0, 0, %r0, 0
+
+ cdgbra %f0, 0, %r0, 0
+
+#CHECK: error: instruction requires: fp-extension
#CHECK: cdlfbr %f0, 0, %r0, 0
cdlfbr %f0, 0, %r0, 0
@@ -465,6 +475,16 @@
ceb %f0, 4096
#CHECK: error: instruction requires: fp-extension
+#CHECK: cefbra %f0, 0, %r0, 0
+
+ cefbra %f0, 0, %r0, 0
+
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cegbra %f0, 0, %r0, 0
+
+ cegbra %f0, 0, %r0, 0
+
+#CHECK: error: instruction requires: fp-extension
#CHECK: celfbr %f0, 0, %r0, 0
celfbr %f0, 0, %r0, 0
@@ -482,6 +502,11 @@
cfdbr %r0, -1, %f0
cfdbr %r0, 16, %f0
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cfdbra %r0, 0, %f0, 0
+
+ cfdbra %r0, 0, %f0, 0
+
#CHECK: error: invalid operand
#CHECK: cfebr %r0, -1, %f0
#CHECK: error: invalid operand
@@ -490,6 +515,11 @@
cfebr %r0, -1, %f0
cfebr %r0, 16, %f0
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cfebra %r0, 0, %f0, 0
+
+ cfebra %r0, 0, %f0, 0
+
#CHECK: error: invalid operand
#CHECK: cfi %r0, (-1 << 31) - 1
#CHECK: error: invalid operand
@@ -509,6 +539,10 @@
cfxbr %r0, 16, %f0
cfxbr %r0, 0, %f2
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cfxbra %r0, 0, %f0, 0
+
+ cfxbra %r0, 0, %f0, 0
#CHECK: error: invalid operand
#CHECK: cg %r0, -524289
@@ -526,6 +560,11 @@
cgdbr %r0, -1, %f0
cgdbr %r0, 16, %f0
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cgdbra %r0, 0, %f0, 0
+
+ cgdbra %r0, 0, %f0, 0
+
#CHECK: error: invalid operand
#CHECK: cgebr %r0, -1, %f0
#CHECK: error: invalid operand
@@ -534,6 +573,11 @@
cgebr %r0, -1, %f0
cgebr %r0, 16, %f0
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cgebra %r0, 0, %f0, 0
+
+ cgebra %r0, 0, %f0, 0
+
#CHECK: error: invalid operand
#CHECK: cgf %r0, -524289
#CHECK: error: invalid operand
@@ -713,6 +757,10 @@
cgxbr %r0, 16, %f0
cgxbr %r0, 0, %f2
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cgxbra %r0, 0, %f0, 0
+
+ cgxbra %r0, 0, %f0, 0
#CHECK: error: invalid operand
#CHECK: ch %r0, -1
@@ -1360,12 +1408,22 @@
cxfbr %f2, %r0
+#CHECK: error: instruction requires: fp-extension
+#CHECK: cxfbra %f0, 0, %r0, 0
+
+ cxfbra %f0, 0, %r0, 0
+
#CHECK: error: invalid register pair
#CHECK: cxgbr %f2, %r0
cxgbr %f2, %r0
#CHECK: error: instruction requires: fp-extension
+#CHECK: cxgbra %f0, 0, %r0, 0
+
+ cxgbra %f0, 0, %r0, 0
+
+#CHECK: error: instruction requires: fp-extension
#CHECK: cxlfbr %f0, 0, %r0, 0
cxlfbr %f0, 0, %r0, 0
diff --git a/llvm/test/MC/SystemZ/insn-good-z196.s b/llvm/test/MC/SystemZ/insn-good-z196.s
index 0ba68c8d010..5ac80156ecf 100644
--- a/llvm/test/MC/SystemZ/insn-good-z196.s
+++ b/llvm/test/MC/SystemZ/insn-good-z196.s
@@ -136,6 +136,34 @@
ark %r15,%r0,%r0
ark %r7,%r8,%r9
+#CHECK: cdfbra %f0, 0, %r0, 0 # encoding: [0xb3,0x95,0x00,0x00]
+#CHECK: cdfbra %f0, 0, %r0, 15 # encoding: [0xb3,0x95,0x0f,0x00]
+#CHECK: cdfbra %f0, 0, %r15, 0 # encoding: [0xb3,0x95,0x00,0x0f]
+#CHECK: cdfbra %f0, 15, %r0, 0 # encoding: [0xb3,0x95,0xf0,0x00]
+#CHECK: cdfbra %f4, 5, %r6, 7 # encoding: [0xb3,0x95,0x57,0x46]
+#CHECK: cdfbra %f15, 0, %r0, 0 # encoding: [0xb3,0x95,0x00,0xf0]
+
+ cdfbra %f0, 0, %r0, 0
+ cdfbra %f0, 0, %r0, 15
+ cdfbra %f0, 0, %r15, 0
+ cdfbra %f0, 15, %r0, 0
+ cdfbra %f4, 5, %r6, 7
+ cdfbra %f15, 0, %r0, 0
+
+#CHECK: cdgbra %f0, 0, %r0, 0 # encoding: [0xb3,0xa5,0x00,0x00]
+#CHECK: cdgbra %f0, 0, %r0, 15 # encoding: [0xb3,0xa5,0x0f,0x00]
+#CHECK: cdgbra %f0, 0, %r15, 0 # encoding: [0xb3,0xa5,0x00,0x0f]
+#CHECK: cdgbra %f0, 15, %r0, 0 # encoding: [0xb3,0xa5,0xf0,0x00]
+#CHECK: cdgbra %f4, 5, %r6, 7 # encoding: [0xb3,0xa5,0x57,0x46]
+#CHECK: cdgbra %f15, 0, %r0, 0 # encoding: [0xb3,0xa5,0x00,0xf0]
+
+ cdgbra %f0, 0, %r0, 0
+ cdgbra %f0, 0, %r0, 15
+ cdgbra %f0, 0, %r15, 0
+ cdgbra %f0, 15, %r0, 0
+ cdgbra %f4, 5, %r6, 7
+ cdgbra %f15, 0, %r0, 0
+
#CHECK: cdlfbr %f0, 0, %r0, 0 # encoding: [0xb3,0x91,0x00,0x00]
#CHECK: cdlfbr %f0, 0, %r0, 15 # encoding: [0xb3,0x91,0x0f,0x00]
#CHECK: cdlfbr %f0, 0, %r15, 0 # encoding: [0xb3,0x91,0x00,0x0f]
@@ -164,6 +192,34 @@
cdlgbr %f4, 5, %r6, 7
cdlgbr %f15, 0, %r0, 0
+#CHECK: cefbra %f0, 0, %r0, 0 # encoding: [0xb3,0x94,0x00,0x00]
+#CHECK: cefbra %f0, 0, %r0, 15 # encoding: [0xb3,0x94,0x0f,0x00]
+#CHECK: cefbra %f0, 0, %r15, 0 # encoding: [0xb3,0x94,0x00,0x0f]
+#CHECK: cefbra %f0, 15, %r0, 0 # encoding: [0xb3,0x94,0xf0,0x00]
+#CHECK: cefbra %f4, 5, %r6, 7 # encoding: [0xb3,0x94,0x57,0x46]
+#CHECK: cefbra %f15, 0, %r0, 0 # encoding: [0xb3,0x94,0x00,0xf0]
+
+ cefbra %f0, 0, %r0, 0
+ cefbra %f0, 0, %r0, 15
+ cefbra %f0, 0, %r15, 0
+ cefbra %f0, 15, %r0, 0
+ cefbra %f4, 5, %r6, 7
+ cefbra %f15, 0, %r0, 0
+
+#CHECK: cegbra %f0, 0, %r0, 0 # encoding: [0xb3,0xa4,0x00,0x00]
+#CHECK: cegbra %f0, 0, %r0, 15 # encoding: [0xb3,0xa4,0x0f,0x00]
+#CHECK: cegbra %f0, 0, %r15, 0 # encoding: [0xb3,0xa4,0x00,0x0f]
+#CHECK: cegbra %f0, 15, %r0, 0 # encoding: [0xb3,0xa4,0xf0,0x00]
+#CHECK: cegbra %f4, 5, %r6, 7 # encoding: [0xb3,0xa4,0x57,0x46]
+#CHECK: cegbra %f15, 0, %r0, 0 # encoding: [0xb3,0xa4,0x00,0xf0]
+
+ cegbra %f0, 0, %r0, 0
+ cegbra %f0, 0, %r0, 15
+ cegbra %f0, 0, %r15, 0
+ cegbra %f0, 15, %r0, 0
+ cegbra %f4, 5, %r6, 7
+ cegbra %f15, 0, %r0, 0
+
#CHECK: celfbr %f0, 0, %r0, 0 # encoding: [0xb3,0x90,0x00,0x00]
#CHECK: celfbr %f0, 0, %r0, 15 # encoding: [0xb3,0x90,0x0f,0x00]
#CHECK: celfbr %f0, 0, %r15, 0 # encoding: [0xb3,0x90,0x00,0x0f]
@@ -192,6 +248,90 @@
celgbr %f4, 5, %r6, 7
celgbr %f15, 0, %r0, 0
+#CHECK: cfdbra %r0, 0, %f0, 0 # encoding: [0xb3,0x99,0x00,0x00]
+#CHECK: cfdbra %r0, 0, %f0, 15 # encoding: [0xb3,0x99,0x0f,0x00]
+#CHECK: cfdbra %r0, 0, %f15, 0 # encoding: [0xb3,0x99,0x00,0x0f]
+#CHECK: cfdbra %r0, 15, %f0, 0 # encoding: [0xb3,0x99,0xf0,0x00]
+#CHECK: cfdbra %r4, 5, %f6, 7 # encoding: [0xb3,0x99,0x57,0x46]
+#CHECK: cfdbra %r15, 0, %f0, 0 # encoding: [0xb3,0x99,0x00,0xf0]
+
+ cfdbra %r0, 0, %f0, 0
+ cfdbra %r0, 0, %f0, 15
+ cfdbra %r0, 0, %f15, 0
+ cfdbra %r0, 15, %f0, 0
+ cfdbra %r4, 5, %f6, 7
+ cfdbra %r15, 0, %f0, 0
+
+#CHECK: cfebra %r0, 0, %f0, 0 # encoding: [0xb3,0x98,0x00,0x00]
+#CHECK: cfebra %r0, 0, %f0, 15 # encoding: [0xb3,0x98,0x0f,0x00]
+#CHECK: cfebra %r0, 0, %f15, 0 # encoding: [0xb3,0x98,0x00,0x0f]
+#CHECK: cfebra %r0, 15, %f0, 0 # encoding: [0xb3,0x98,0xf0,0x00]
+#CHECK: cfebra %r4, 5, %f6, 7 # encoding: [0xb3,0x98,0x57,0x46]
+#CHECK: cfebra %r15, 0, %f0, 0 # encoding: [0xb3,0x98,0x00,0xf0]
+
+ cfebra %r0, 0, %f0, 0
+ cfebra %r0, 0, %f0, 15
+ cfebra %r0, 0, %f15, 0
+ cfebra %r0, 15, %f0, 0
+ cfebra %r4, 5, %f6, 7
+ cfebra %r15, 0, %f0, 0
+
+#CHECK: cfxbra %r0, 0, %f0, 0 # encoding: [0xb3,0x9a,0x00,0x00]
+#CHECK: cfxbra %r0, 0, %f0, 15 # encoding: [0xb3,0x9a,0x0f,0x00]
+#CHECK: cfxbra %r0, 0, %f13, 0 # encoding: [0xb3,0x9a,0x00,0x0d]
+#CHECK: cfxbra %r0, 15, %f0, 0 # encoding: [0xb3,0x9a,0xf0,0x00]
+#CHECK: cfxbra %r7, 5, %f8, 9 # encoding: [0xb3,0x9a,0x59,0x78]
+#CHECK: cfxbra %r15, 0, %f0, 0 # encoding: [0xb3,0x9a,0x00,0xf0]
+
+ cfxbra %r0, 0, %f0, 0
+ cfxbra %r0, 0, %f0, 15
+ cfxbra %r0, 0, %f13, 0
+ cfxbra %r0, 15, %f0, 0
+ cfxbra %r7, 5, %f8, 9
+ cfxbra %r15, 0, %f0, 0
+
+#CHECK: cgdbra %r0, 0, %f0, 0 # encoding: [0xb3,0xa9,0x00,0x00]
+#CHECK: cgdbra %r0, 0, %f0, 15 # encoding: [0xb3,0xa9,0x0f,0x00]
+#CHECK: cgdbra %r0, 0, %f15, 0 # encoding: [0xb3,0xa9,0x00,0x0f]
+#CHECK: cgdbra %r0, 15, %f0, 0 # encoding: [0xb3,0xa9,0xf0,0x00]
+#CHECK: cgdbra %r4, 5, %f6, 7 # encoding: [0xb3,0xa9,0x57,0x46]
+#CHECK: cgdbra %r15, 0, %f0, 0 # encoding: [0xb3,0xa9,0x00,0xf0]
+
+ cgdbra %r0, 0, %f0, 0
+ cgdbra %r0, 0, %f0, 15
+ cgdbra %r0, 0, %f15, 0
+ cgdbra %r0, 15, %f0, 0
+ cgdbra %r4, 5, %f6, 7
+ cgdbra %r15, 0, %f0, 0
+
+#CHECK: cgebra %r0, 0, %f0, 0 # encoding: [0xb3,0xa8,0x00,0x00]
+#CHECK: cgebra %r0, 0, %f0, 15 # encoding: [0xb3,0xa8,0x0f,0x00]
+#CHECK: cgebra %r0, 0, %f15, 0 # encoding: [0xb3,0xa8,0x00,0x0f]
+#CHECK: cgebra %r0, 15, %f0, 0 # encoding: [0xb3,0xa8,0xf0,0x00]
+#CHECK: cgebra %r4, 5, %f6, 7 # encoding: [0xb3,0xa8,0x57,0x46]
+#CHECK: cgebra %r15, 0, %f0, 0 # encoding: [0xb3,0xa8,0x00,0xf0]
+
+ cgebra %r0, 0, %f0, 0
+ cgebra %r0, 0, %f0, 15
+ cgebra %r0, 0, %f15, 0
+ cgebra %r0, 15, %f0, 0
+ cgebra %r4, 5, %f6, 7
+ cgebra %r15, 0, %f0, 0
+
+#CHECK: cgxbra %r0, 0, %f0, 0 # encoding: [0xb3,0xaa,0x00,0x00]
+#CHECK: cgxbra %r0, 0, %f0, 15 # encoding: [0xb3,0xaa,0x0f,0x00]
+#CHECK: cgxbra %r0, 0, %f13, 0 # encoding: [0xb3,0xaa,0x00,0x0d]
+#CHECK: cgxbra %r0, 15, %f0, 0 # encoding: [0xb3,0xaa,0xf0,0x00]
+#CHECK: cgxbra %r7, 5, %f8, 9 # encoding: [0xb3,0xaa,0x59,0x78]
+#CHECK: cgxbra %r15, 0, %f0, 0 # encoding: [0xb3,0xaa,0x00,0xf0]
+
+ cgxbra %r0, 0, %f0, 0
+ cgxbra %r0, 0, %f0, 15
+ cgxbra %r0, 0, %f13, 0
+ cgxbra %r0, 15, %f0, 0
+ cgxbra %r7, 5, %f8, 9
+ cgxbra %r15, 0, %f0, 0
+
#CHECK: chf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xcd]
#CHECK: chf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xcd]
#CHECK: chf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xcd]
@@ -344,6 +484,34 @@
clih %r0, (1 << 32) - 1
clih %r15, 0
+#CHECK: cxfbra %f0, 0, %r0, 0 # encoding: [0xb3,0x96,0x00,0x00]
+#CHECK: cxfbra %f0, 0, %r0, 15 # encoding: [0xb3,0x96,0x0f,0x00]
+#CHECK: cxfbra %f0, 0, %r15, 0 # encoding: [0xb3,0x96,0x00,0x0f]
+#CHECK: cxfbra %f0, 15, %r0, 0 # encoding: [0xb3,0x96,0xf0,0x00]
+#CHECK: cxfbra %f4, 5, %r9, 10 # encoding: [0xb3,0x96,0x5a,0x49]
+#CHECK: cxfbra %f13, 0, %r0, 0 # encoding: [0xb3,0x96,0x00,0xd0]
+
+ cxfbra %f0, 0, %r0, 0
+ cxfbra %f0, 0, %r0, 15
+ cxfbra %f0, 0, %r15, 0
+ cxfbra %f0, 15, %r0, 0
+ cxfbra %f4, 5, %r9, 10
+ cxfbra %f13, 0, %r0, 0
+
+#CHECK: cxgbra %f0, 0, %r0, 0 # encoding: [0xb3,0xa6,0x00,0x00]
+#CHECK: cxgbra %f0, 0, %r0, 15 # encoding: [0xb3,0xa6,0x0f,0x00]
+#CHECK: cxgbra %f0, 0, %r15, 0 # encoding: [0xb3,0xa6,0x00,0x0f]
+#CHECK: cxgbra %f0, 15, %r0, 0 # encoding: [0xb3,0xa6,0xf0,0x00]
+#CHECK: cxgbra %f4, 5, %r9, 10 # encoding: [0xb3,0xa6,0x5a,0x49]
+#CHECK: cxgbra %f13, 0, %r0, 0 # encoding: [0xb3,0xa6,0x00,0xd0]
+
+ cxgbra %f0, 0, %r0, 0
+ cxgbra %f0, 0, %r0, 15
+ cxgbra %f0, 0, %r15, 0
+ cxgbra %f0, 15, %r0, 0
+ cxgbra %f4, 5, %r9, 10
+ cxgbra %f13, 0, %r0, 0
+
#CHECK: cxlfbr %f0, 0, %r0, 0 # encoding: [0xb3,0x92,0x00,0x00]
#CHECK: cxlfbr %f0, 0, %r0, 15 # encoding: [0xb3,0x92,0x0f,0x00]
#CHECK: cxlfbr %f0, 0, %r15, 0 # encoding: [0xb3,0x92,0x00,0x0f]
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