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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2017-05-15 12:37:03 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2017-05-15 12:37:03 +0000 |
| commit | 03852a9dcaff24251fe73c2dfc5a0cc008170e54 (patch) | |
| tree | 44ea1a9c18bd14b6f63d4e6832657131843b669d | |
| parent | 9486becf09fd8ca849066bf70f9cbb0bb3716181 (diff) | |
| download | bcm5719-llvm-03852a9dcaff24251fe73c2dfc5a0cc008170e54.tar.gz bcm5719-llvm-03852a9dcaff24251fe73c2dfc5a0cc008170e54.zip | |
[AMDGPU][MC] Removed V_MQSAD_U16_U8
This instruction does not really exist
See Bug 33018: https://bugs.llvm.org//show_bug.cgi?id=33018
Reviewers: vpykhtin, artem.tamazov
Differential Revision: https://reviews.llvm.org/D33126
llvm-svn: 303055
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP3Instructions.td | 3 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt | 18 |
2 files changed, 18 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 217a0748885..ffa6c60d6b1 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -232,7 +232,6 @@ def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>; let SubtargetPredicate = isCIVI in { -def V_MQSAD_U16_U8 : VOP3Inst <"v_mqsad_u16_u8", VOP3_Profile<VOP_I32_I32_I32>>; def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_qsad_pk_u16_u8>; def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32>, int_amdgcn_mqsad_u32_u8>; @@ -402,7 +401,6 @@ multiclass VOP3be_Real_ci<bits<9> op> { } } -defm V_MQSAD_U16_U8 : VOP3_Real_ci <0x172>; defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>; defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x175>; defm V_MAD_U64_U32 : VOP3be_Real_ci <0x176>; @@ -426,7 +424,6 @@ multiclass VOP3be_Real_vi<bits<10> op> { } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI" -defm V_MQSAD_U16_U8 : VOP3_Real_vi <0x172>; defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt index c15fbaa1e3a..a1cc1f06c3c 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt @@ -81,6 +81,24 @@ # VI: v_clrexcp ; encoding: [0x00,0x00,0x75,0xd1,0x00,0x00,0x00,0x00] 0x00 0x00 0x75 0xd1 0x00 0x00 0x00 0x00 +# VI: v_fract_f64_e64 v[5:6], s[2:3] ; encoding: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x00] +0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x00 + +# VI: v_fract_f64_e64 v[5:6], -4.0 ; encoding: [0x05,0x00,0x72,0xd1,0xf7,0x00,0x00,0x00] +0x05,0x00,0x72,0xd1,0xf7,0x00,0x00,0x00 + +# VI: v_fract_f64_e64 v[5:6], -s[2:3] ; encoding: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x20] +0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x20 + +# VI: v_fract_f64_e64 v[5:6], |s[2:3]| ; encoding: [0x05,0x01,0x72,0xd1,0x02,0x00,0x00,0x00] +0x05,0x01,0x72,0xd1,0x02,0x00,0x00,0x00 + +# VI: v_fract_f64_e64 v[5:6], s[2:3] clamp ; encoding: [0x05,0x80,0x72,0xd1,0x02,0x00,0x00,0x00] +0x05,0x80,0x72,0xd1,0x02,0x00,0x00,0x00 + +# VI: v_fract_f64_e64 v[5:6], s[2:3] mul:2 ; encoding: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x08] +0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x08 + # VI: v_fract_f32_e64 v1, -v2 ; encoding: [0x01,0x00,0x5b,0xd1,0x02,0x01,0x00,0x20] 0x01 0x00 0x5b 0xd1 0x02 0x01 0x00 0x20 |
