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author | Quentin Colombet <qcolombet@apple.com> | 2014-08-07 00:20:44 +0000 |
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committer | Quentin Colombet <qcolombet@apple.com> | 2014-08-07 00:20:44 +0000 |
commit | 0233d4957443d8b07368eb0dca6ee77de8977a23 (patch) | |
tree | 97a4c3683e919820a66dd00d02905d141258d7f6 | |
parent | 4f1fc35b1312c05f1ba49722f20ea4d86dd5bb1f (diff) | |
download | bcm5719-llvm-0233d4957443d8b07368eb0dca6ee77de8977a23.tar.gz bcm5719-llvm-0233d4957443d8b07368eb0dca6ee77de8977a23.zip |
[X86][SchedModel] Fixed missing/wrong scheduling model found by code inspection.
Source: Agner Fog's Instruction tables.
Related to <rdar://problem/15607571>
llvm-svn: 215045
-rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 4 | ||||
-rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index abc244b34a2..9001fbaa894 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -199,11 +199,11 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2), asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], - NoItinerary, d>; + NoItinerary, d>, Sched<[WriteCvtI2F]>; def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins DstRC:$src1, x86memop:$src2), asm, [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], - NoItinerary, d>; + NoItinerary, d>, Sched<[WriteCvtI2FLd]>; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 46bf9b8a9f2..ea8b6c7cf43 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -1017,7 +1017,7 @@ def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), // For disassembler let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, - SchedRW = [WriteMove] in { + SchedRW = [WriteFShuffle] in { def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src), "movaps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>; |