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author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:16:08 +0000 |
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committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:16:08 +0000 |
commit | 0024b8bd73528a3cdd764152459c9990f13b4093 (patch) | |
tree | 2144cd5e73f561122e3b75e65c29002f6effbefc | |
parent | 89901730b1f432844d79dffc109b81c0d1b0f979 (diff) | |
download | bcm5719-llvm-0024b8bd73528a3cdd764152459c9990f13b4093.tar.gz bcm5719-llvm-0024b8bd73528a3cdd764152459c9990f13b4093.zip |
ARM sched model: Add VFP div instruction on Swift
llvm-svn: 183271
-rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleSwift.td | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleSwift.td b/llvm/lib/Target/ARM/ARMScheduleSwift.td index 77d464bdb95..be7f76feb44 100644 --- a/llvm/lib/Target/ARM/ARMScheduleSwift.td +++ b/llvm/lib/Target/ARM/ARMScheduleSwift.td @@ -2042,6 +2042,22 @@ let SchedModel = SwiftModel in { (instregex "VST4LN(d|q)(8|16|32)_UPD", "VST4LN(d|q)(8|16|32)Pseudo_UPD")>; + // 4.2.44 VFP, Divide and Square Root + def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { + let NumMicroOps = 1; + let Latency = 17; + let ResourceCycles = [1, 15]; + } + def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { + let NumMicroOps = 1; + let Latency = 32; + let ResourceCycles = [1, 30]; + } + def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>; + def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>; + + // Not specified. + def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>; // Preload. def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0; let ResourceCycles = [0]; |