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| author | Craig Topper <craig.topper@intel.com> | 2017-10-01 23:53:50 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-01 23:53:50 +0000 |
| commit | 00230604d399003acc2ac13c044535ae6b7768ee (patch) | |
| tree | 11341d1cec535dc32277588c2cee56173a05a643 | |
| parent | 43ca7167ad74fc49e75989db2830236d260c52e4 (diff) | |
| download | bcm5719-llvm-00230604d399003acc2ac13c044535ae6b7768ee.tar.gz bcm5719-llvm-00230604d399003acc2ac13c044535ae6b7768ee.zip | |
[X86] Remove a couple unnecessary COPY_TO_REGCLASS from some output patterns where the instruction already produces the correct register class.
llvm-svn: 314638
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 6eb9607bb9d..7be8d4568f6 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -3391,21 +3391,19 @@ def : Pat<(_.VT (OpNode _.RC:$src0, (_.EltVT (X86selects (scalar_to_vector (and (i8 (trunc GR32:$mask)), (i8 1))), (_.EltVT _.FRC:$src1), (_.EltVT _.FRC:$src2))))))), - (COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrk) - (COPY_TO_REGCLASS _.FRC:$src2, _.RC), - (COPY_TO_REGCLASS GR32:$mask, VK1WM), - (_.VT _.RC:$src0), _.FRC:$src1), - _.RC)>; + (!cast<Instruction>(InstrStr#rrk) + (COPY_TO_REGCLASS _.FRC:$src2, _.RC), + (COPY_TO_REGCLASS GR32:$mask, VK1WM), + (_.VT _.RC:$src0), _.FRC:$src1)>; def : Pat<(_.VT (OpNode _.RC:$src0, (_.VT (scalar_to_vector (_.EltVT (X86selects (scalar_to_vector (and (i8 (trunc GR32:$mask)), (i8 1))), (_.EltVT _.FRC:$src1), (_.EltVT ZeroFP))))))), - (COPY_TO_REGCLASS (!cast<Instruction>(InstrStr#rrkz) - (COPY_TO_REGCLASS GR32:$mask, VK1WM), - (_.VT _.RC:$src0), _.FRC:$src1), - _.RC)>; + (!cast<Instruction>(InstrStr#rrkz) + (COPY_TO_REGCLASS GR32:$mask, VK1WM), + (_.VT _.RC:$src0), _.FRC:$src1)>; } multiclass avx512_store_scalar_lowering<string InstrStr, AVX512VLVectorVTInfo _, |
